User`s manual

4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
5-26 EPSON APPLICATION NOTES (S19A-G-005-05)
4.2.3 Memory Controller Module
General-Purpose Chip Select Module (GPCM)
The General-Purpose Chip Select Module (GPCM) is used to control memory and peripheral
devices which do not require special timing or address multiplexing. In addition to the chip select
output, it can generate active-low Output Enable (OE
) and Write Enable (WE) signals compatible
with most memory and x86-style peripherals. The MPC821 bus controller also provides a Read/
Write (RD/WR
) signal which is compatible with most 68K peripherals.
The GPCM is controlled by the values programmed into the Base Register (BR) and Option Register
(OR) of the respective chip select. In addition to setting the base address and block size of the chip
select, the option register allows control over several timing parameters:
• The ACS bit field allows the chip select assertion to be delayed with respect to the address bus
valid, by 0, 1/4, or 1/2 clock cycle.
• The CSNT bit causes chip select and WE to be negated 1/2 clock cycle earlier than normal.
• The TRLX (Relaxed timing) bit will insert an additional 1 clock delay between assertion of the
address bus and chip select, to accommodate memories and peripherals with long setup times.
• The EHTR (Extended hold time) bit will insert an additional 1-clock delay on the first access to a
chip select.
• Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself by assert-
ing TA (Transfer Acknowledge).
• Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its memory
space is addressed by the processor core.
User-Programmable Machine (UPM)
The UPM is typically used to control memories, such as Dynamic RAMs, which have complex con-
trol or address multiplexing requirements. The UPM is a general purpose RAM-based pattern gener-
ator which can control address multiplexing, wait state generation, and five general-purpose output
lines on the MPC821. Up to 64 pattern locations are available, each 32 bits wide. Separate patterns
may be programmed for normal accesses, burst accesses, refresh (timer) events, and exception con-
ditions. Because of this flexibility, almost any type of memory or peripheral device may be accom-
modated by the MPC821.
In this application note, the GPCM is used instead of the UPM, since the GPCM has enough flexibil-
ity to accommodate the S1D13504 and it is desirable to leave the UPMs free to handle other inter-
facing duties, such as EDO DRAM.