User`s manual

4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
5-32 EPSON APPLICATION NOTES (S19A-G-005-05)
4.4.3 MPC821 Chip Select Configuration
The DRAM on the MPC821 ADS board extends from address 0 through 0x3fffff, so the S1D13504
is addressed starting at 0x400000. A total of 4M bytes of address space is used, where the lower 2M
bytes is reserved for the S1D13504 on-chip registers and the upper 2M bytes is used to access the
S1D13504 display buffer.
Chip select 4 is used to control the S1D13504. The following options are selected in the base address
register (BR4):
• BA (0:16) = 0000 0000 0100 0000 0 – set starting address of S1D13504 to 0x40 0000
• AT (0:2) = 0 – ignore address type bits
• PS (0:1) = 1:0 – memory port size is 16 bits
• PARE = 0 – disable parity checking
• WP = 0 – disable write protect
• MS (0:1) = 0:0 – select General Purpose Chip Select module to control this chip select
• V = 1 – set valid bit to enable chip select
The following options were selected in the option register (OR4):
• AM (0:16) = 1111 1111 1100 0000 0 – mask all but upper 10 address bits; S1D13504 consumes
4M byte of address space
• ATM (0:2) = 0 – ignore address type bits
• CSNT = 0 – normal CS/WE negation
• ACS (0:1) = 1:1 – delay CS assertion by 1/2 clock cycle from address lines
• BI = 1 – assert Burst Inhibit
• SCY (0:3) = 0 – wait state selection; this field is ignored since external transfer acknowledge is
used; see SETA below
• SETA = 1 – the S1D13504 generates an external transfer acknowledge using the WAIT# line
• TRLX = 0 – normal timing
• EHTR = 0 – normal timing