User`s manual

6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR
APPLICATION NOTES (S19A-G-005-05) EPSON 5-47
6.3 System Design Using the IT8368E PC Card Buffer
If the system designer uses an ITE IT8368E PC Card and multiple-function IO buffer, the
S1D13504 can be interfaced with the TX3912 without using a PC Card slot. Instead, the S1D13504
is mapped to a rarely-used 16M byte portion of the PC Card slot buffered by the IT8368E. This
makes the S1D13504 virtually transparent to PC Card devices that use the same slot.
6.3.1 Hardware Description—Using One IT8368E
The ITE IT8368E has been specifically designed to support EPSON CRT/LCD controllers. The
IT8368E provides eleven Multi-Function IO pins (MFIO). Configuration registers can be used to
allow these MFIO pins to provide the control signals required to implement the S1D13504 CPU
interface.
The Toshiba TX3912 processor only provides addresses A[12:0], therefore devices that occupy more
address space must use an external device to latch A[25:13]. The IT8368E’s MFIO pins can be con-
figured to provide this latched address. However, when using the S1D13504, five MFIO pins are uti-
lized for S1D13504 control signals and cannot provide latched addresses. In this case, an external
latch must be used to provide the high-order address bits. For a solution that does not require a latch,
refer to Section 1.3.2, “Hardware Description—Using Two IT8368E’s” on page 5.
Figure 6-2 S1D13504 to TX3912 Connection using One IT8368E
Note: The Chip Select Logic shown above is necessary to guarantee timing parameter t1
of the Generic MPU Interface Asynchronous Timing (for details refer to the “S1D13504 Hardware
Functional Specification”, document number S19A-A-002-xx).
HA[12:0]
ENDIAN
ALE
HD[31:24]
HD[23:16]
CARDxWAIT*
DCLKOUT
IO VDD, CORE VDD
AB[12:0]
AB[20:13]
DB[7:0]
DB[15:8]
RESET#
WAIT#
M/R#
CLKI
BUSCLK
WE1#
WE0#
RD1#
RD0#
CS#
TX3912
LHA[23]/MFIO[10]
LHA[22]/MFIO[9]
LHA[21]/MFIO[8]
LHA[20]/MFIO[7]
LHA[19]/MFIO[6]
IT8368E
S1D13504
Latch
Chip Select Logic
A23
+3.3V
System RESET
Pull-up
VDD
Clock
divider
Oscillator
... or ...
See text