User`s manual

6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR
5-48 EPSON APPLICATION NOTES (S19A-G-005-05)
The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to
the S1D13504 bus clock. This gives the system designer full flexibility in choosing the appropriate
source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and
whether to use DCLKOUT (divided) as the clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13504 clock frequencies.
The S1D13504 also has internal clock dividers providing additional flexibility.
6.3.2 Hardware Description—Using Two IT8368E’s
The following implementation uses a second IT8368E, not in VGA mode, in place of an address
latch. The pins LHA[23] and LHA[20:13] provide the latch function instead.
Figure 6-3 S1D13504 to TX3912 Connection using Two IT8368E
The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to
the S1D13504 bus clock. This gives the system designer full flexibility in choosing the appropriate
source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and
whether to use DCLKOUT (divided) as the clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13504 clock frequencies.
The S1D13504 also has internal clock dividers providing additional flexibility.
Note: The Chip Select Logic shown above is necessary to guarantee the timing parameter t1
of the Generic MPU Host Bus Interface Asynchronous Timing (for details refer to the
“S1D13504 Hardware Functional Specification”, document number S19A-A-002-xx).
HA[12:0]
ENDIAN
HD[31:24]
HD[23:16]
CARDxWAIT*
DCLKOUT
AB[12:0]
AB[20:13]
DB[7:0]
DB[15:8]
RESET#
WAIT#
M/R#
BUSCLK
CLKI
IO VDD, CORE VDD
WE1#
WE0#
RD1#
RD0#
CS#
TX3912
LHA[23]/MFIO[10]
LHA[22]/MFIO[9]
LHA[21]/MFIO[8]
LHA[20]/MFIO[7]
LHA[19]/MFIO[6]
IT8368E
LHA[20:13],
LHA23
IT8368E
S1D13504
Chip Select Logic
LHA23
+3.3V
System RESET
Pull-up
VDD
Clock
divider
Oscillator
... or ...
See text