User`s manual

7: A.C. CHARACTERISTICS
1-24 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL
SPECIFICATION (X19A-A-002-17)
7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030)
Figure 7-5 MC68030 Bus 2 Interface Timing
Note: 1. If the S1D13504 host interface is disabled, the timing for DSACK1# driven high is relative to the
falling edge of AS# or
the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever
one is later.
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes valid,
whichever occurs later.
Table 7-5 MC68030 Bus 2 Interface Timing
Symbol Parameter
5V
Units
Min. Max.
t1
Clock period 30 ns
t2
Clock pulse width high 5 ns
t3
Clock pulse width low 5 ns
t4
A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# = 0, and either UDS#=0 or
LDS# = 0
4ns
t5
A[20:0], SIZ[1:0], M/R# hold from AS# 0 ns
t6
1
CS# hold from AS# 0 ns
t7
R/W# setup to DS# 5 ns
t8
R/W# hold from AS# 0 ns
t9
AS# = 0 and CS# = 0 to DSACK1# driven high 1 5 ns
t10
AS# high to DSACK1# high impedance 1 ns
t11
D[31:16] valid to second CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0
(write cycle)
0ns
t12
D[31:16] hold from falling edge of DSACK1# (write cycle) 0 ns
t13
Falling edge of UDS# = 0 or LDS# = 0 to D[31:16] driven (read cycle) 3 ns
t14
D[31:16] valid to DSACK1# falling edge (read cycle) 0 ns
t15
UDS# and LDS# high to D[31:16] invalid/high impedance (read cycle) 2 11 ns
t16
AS# high setup to CLK 3 ns
A[20:0]
AS#
DS#
D[31:16](write)
SIZ[1:0] M/R#
R/W#
DSACK1#
CLK
t1 t2 t3
t4
t10
t7
CS#
t6
t8
t5
D[31:16](read)
t11
t12
t9
t13 t14
t15
t16