User`s manual

7: A.C. CHARACTERISTICS
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-25
SPECIFICATION (X19A-A-002-17)
Figure 7-6 MC68030 Read Bus Timing
Note: 1 .If the S1D13504 host interface is disabled, the timing for DSACK1# driven high is relative to the
falling edge of AS# or
the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever
one is later.
Table 7-6 MC68030 Read Bus Timing
Symbol Parameter
5V
Units
Min. Max.
TCLK Bus clock period 30 ns
t1
A[20:0], CS#, M/R#, SIZ0, SIZ1 valid before AS#, DS# falling edge 5 ns
t2
A[20:0], CS#, M/R#, SIZ0, SIZ1 hold from AS#, DS# rising edge 5 ns
t3
R/W# rising edge to AS#, DS# falling edge 5 ns
t4
1
AS# low to DSACK1# driven high 7 ns
t5
CLK to DSACK1# low 14 ns
t6
AS# high to DSACK1# high impedance 5 ns
t7
AS#, DS# falling edge to D[31:16] 12 ns
t8
Read Data valid to DSACK1# low 0 ns
t9
AS#, DS# rising edge to D[31:16] high impedance 11 ns
t8
Valid
Valid
t1
t9
t2
Hi-Z
Hi-Z
t3
t6
t4
t5
t7
A[20:0]
AS#
DS#
D[31:16]
R/W#
CS#
SIZ0, SIZ1
CLK
DSACK1#
M/R#
TCLK
Hi-Z
Hi-Z