User`s manual

7: A.C. CHARACTERISTICS
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-27
SPECIFICATION (X19A-A-002-17)
Figure 7-8 Generic Write Bus Synchronous Timing
Note: 1. If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling
edge of CS# and WE0#, WE1# or
the first positive edge of BCLK after A[20:0], M/R# becomes val-
id, whichever one is later.
Table 7-8 Generic Write Bus Synchronous Timing
Symbol Parameter
3.3V
Units
Min. Max.
TBCLK Bus clock period 25 ns
t1
A[20:0], M/R#, CS#, RD0#, RD1# hold time 1 ns
t2
A[20:0], M/R#, CS#, RD0#, RD1# setup time 5 ns
t3
WE0#, WE1# high to A[20:0], CS#, M/R# invalid 0 ns
t4
D[15:0] setup time 5 ns
t5
D[15:0] hold from WE0#, WE1# high 0 ns
t6
1
WE0#, WE1# low and CS# low to WAIT# driven low 7 ns
t7
BCLK to WAIT# high 15 ns
t8
WE0#, WE1# high to WAIT# high impedance 6 ns
t5
t7
t4
t8
BCLK
A[20:0]
CS#
WE0#
D[15:0]
WAIT#
t6
Valid
t3
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Valid
WE1#
M/R#
t1 t2
t1 t2
t1 t2
t1
t2
t1 t2
t1
t2
TBCLK