User`s manual

7: A.C. CHARACTERISTICS
1-28 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL
SPECIFICATION (X19A-A-002-17)
7.1.5 Generic MPU Interface Asynchronous Timing
Figure 7-9 Generic MPU Interface Asynchronous Timing
Note: 1. If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling
edge of CS# or
the first positive edge of BCLK after A[20:0], M/R# becomes valid, whichever one
is later.
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of RD0#, RD1# or
the first positive edge of BCLK after A[20:0], M/R# becomes valid, which-
ever one is later.
Table 7-9 Generic MPU Interface Asynchronous Timing
Symbol Parameter
3.3V
Units
Min. Max.
TBCLK Bus clock period 25 ns
t1
RD0#, RD1#, WE0#, WE1# low to CS# low 4 ns
t2
A[20:0], M/R# valid to RD0#, RD1#, WE0#, WE1# low 0 ns
t3
RD0#, RD1#, WE0#, WE1# high to A[20:0], CS#, M/R# invalid and CS# high 0 ns
t4
1
CS# low to WAIT# driven low 1 7 ns
t5
RD0#, RD1#, WE0#, WE1# high to WAIT# high impedance 1 6 ns
t6
WE0#, WE1# low to D[15:0] valid (write cycle) 20 ns
t7
D[15:0] hold from WE0#, WE1# high (write cycle) 0 ns
t8
2
RD0#, RD1# low to D[15:0] driven (read cycle) 3 15 ns
t9
D[15:0] valid to WAIT# high (read cycle) 0
t10
RD0#, RD1# high to D[15:0] high impedance (read cycle) 2 10
t1
t3
t9
t5
BCLK
A[20:0]
CS#
RD0#,RD1#
D[15:0](read)
WAIT#
t10
t2
t4
Valid
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Valid
t8
WE0#,WE1#
M/R#
TBCLK
t7
t6
D[15:0](write)
Valid
Hi-Z
Hi-Z