User`s manual

7: A.C. CHARACTERISTICS
1-30 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL
SPECIFICATION (X19A-A-002-17)
7.2 Clock Input Requirements
Figure 7-11 Clock Input Requirements
Note: When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).
Table 7-11 Clock Input Requirements
Symbol Parameter Min. Typ. Max. Units
TCLKI Input Clock Period (CLKI) 12.5 ns
TPCLK Pixel Clock Period (PCLK) not shown 25 ns
TMCLK Memory Clock Period (MCLK) not shown 25 ns
tPWH
Input Clock Pulse Width High (CLKI) 45% 55% TCLKI
tPWL
Input Clock Pulse Width Low (CLKI) 45% 55% TCLKI
tPWLtPWH
Clock Input Waveform
TCLKI
VIH
VIL