User`s manual

8: REGISTERS
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-67
SPECIFICATION (X19A-A-002-17)
bits 4–0 Horizontal Non-Display Period Bits [4:0]
These bits specify the horizontal non-display period width in 8-pixel resolution.
Horizontal non-display period width in number of pixels = ((ContentsOfThisRegister) + 1) × 8.
The recommended minimum value which should be programmed into this register is 3
(32 pixels). The maximum value which can be programmed into this register is 1F, which
gives a horizontal non-display period width of 256 pixels.
Note: This register must be programmed such that
REG[05h] ≥ 3 and (REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
bits 4–0 HRTC/FPLINE Start Position Bits [4:0]
For CRTs and TFTs, these bits specify the delay from the start of the horizontal non-dis-
play period to the leading edge of the HRTC pulse and FPLINE pulse respectively.
Contents of this Register = (HRTC/FPLINE Start Position ÷ 8) - 1 .
The maximum HRTC start delay is 256 pixels.
Note: This register must be programmed such that
(REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
bit 7 HRTC Polarity Select
For CRTs, this bit selects the polarity of the HRTC. When this bit = 1, the HRTC pulse is
active high. When this bit = 0, the HRTC pulse is active low.
bit 6 FPLINE Polarity Select
This bit selects the polarity of the FPLINE for TFT and passive LCD. When this bit = 1,
the FPLINE pulse is active high for TFT and active low for passive LCD. When this bit =
0, the FPLINE pulse is active low for TFT and active high for passive LCD.
bits 3–0 HRTC/FPLINE Pulse Width Bits [3:0]
For CRTs and TFTs, these bits specify the pulse width of HRTC and FPLINE respec-
tively. For passive LCDs, FPLINE is automatically created and these bits have no effect.
HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) × 8.
The maximum HRTC pulse width is 128 pixels.
Note: This register must be programmed such that
(REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
Horizontal Non-Display Period Register
REG[05h] RW
n/a n/a n/a
Horizontal
Non-Display
Period Bit 4
Horizontal
Non-Display
Period Bit 3
Horizontal
Non-Display
Period Bit 2
Horizontal
Non-Display
Period Bit 1
Horizontal
Non-Display
Period Bit 0
HRTC/FPLINE Start Position Register
REG[06h] RW
n/a n/a n/a
HRTC/FPLINE
Start Position
Bit 4
HRTC/FPLINE
Start Position
Bit 3
HRTC/FPLINE
Start Position
Bit 2
HRTC/FPLINE
Start Position
Bit 1
HRTC/FPLINE
Start Position
Bit 0
HRTC/FPLINE Pulse Width Register
REG[07h] RW
HRTC
Polarity Select
FPLINE
Polarity Select
n/a n/a
HRTC/FPLINE
Pulse Width Bit
3
HRTC/FPLINE
Pulse Width Bit
2
HRTC/FPLINE
Pulse Width Bit
1
HRTC/FPLINE
Pulse Width Bit
0
Table 8-4 FPLINE Polarity Selection
FPLINE Polarity Select Passive LCD FPLINE Polarity TFT FPLINE Polarity
0 active high active low
1 active low active high