User`s manual

8: REGISTERS
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-75
SPECIFICATION (X19A-A-002-17)
8.2.6 Power Save Configuration Registers
bit 3 LCD Power Disable
When this bit = 1 the LCDPWR output is directly forced to the Off state. The LCDPWR
“On/Off” state is configured by MD10 at the rising edge of RESET#. When this bit = 0
the LCDPWR output is controlled by the panel on/off sequencing logic. See Table 5-8,
“Summary of Power On / Reset Options,” on page 16.
bits 2–1 Suspend Refresh Select Bits [1:0]
These bits specify the type of DRAM refresh to use in Suspend mode.
Note: These bits should not be changed when suspend mode is enabled.
bit 0 Software Suspend Mode Enable
When this bit = 1 software suspend mode is enabled. When this bit = 0 software suspend
mode is disabled.
Power Save Configuration Register
REG[1Ah] RW
n/a n/a n/a n/a
LCD Power
Disable
Suspend
Refresh Select
Bit 1
Suspend
Refresh Select
Bit 0
Software
Suspend Mode
Enable
Table 8-10 Suspend Refresh Selection
Suspend Refresh Select Bits [1:0] DRAM Refresh Type
00 CBR Refresh
01 Self-Refresh
1x No Refresh