Specifications

SED1560 Series
7–20 EPSON
VSS = –5.0 V ±10%, Ta = –30 ~ 85 °C
Item Signal Symbol Conditions Min. Max. Unit
Serial clock cycle SCL
tSCYC 250 ns
SCL High pulse width
tSHW 75 ns
SCL Low pulse width
tSLW 75 ns
Address setup time A0
tSAS 50 ns
Address hold time
tSAH 200 ns
Data setup time SI
tSDS 50 ns
Data hold time
tSDH 30 ns
CS-SCL time
cs tCSS 30 ns
tCSH 400
Input signal change time
tr, tf 50 ns
VSS = –2.7 V ~ –4.5 V, Ta = –30 ~ 85 °C
Item Signal Symbol Conditions Min. Max. Unit
Serial clock cycle SCL
tSCYC 500 ns
SCL High pulse width
tSHW 150 ns
SCL Low pulse width
tSLW 150 ns
Address setup time A0
tSAS 100 ns
Address hold time
tSAH 400 ns
Data setup time SI
tSDS 100 ns
Data hold time
tSDH 100 ns
CS-SCL time
cs tCSS 60 ns
tCSH 800
Input signal change time
tr, tf 50 ns
*1. All signal timings are limited based on the 20% and 80% of V
SS voltage.
*2. When usingin the range of V
SS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.