Specifications
SED1560 Series
7–24 EPSON
Figure 4. Display data RAM addressing
Note
For a 1/65 and 1/33 display duty cycles, page 8 is accessed following 1BH and 3BH, respectively.
Display Data RAM
The display data RAM stores pixel data for the LCD. It
is a 166-column × 65-row addressable array as shown in
figure 4.
Line
address
00H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
DATA
Page
address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
0
Page 1
Page 0
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Common
address
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM I
1/64
Start
1/32
ADC
DO
=1
DO
=0
A5
A4
A3
A2
A1
A0
9F
9E
00
01
02
03
04
05
06
07
LCD
OUT
O0
O1
O2
O3
O4
O5
O6
O7
A2O3
O162
A3
A4
A5
O2
O1
O0
O163
O164
O165
000
0001
0010
0011
0100
0101
0110
0111
1000
to
to
to
Column address
(If the display start line is set to 1ch)