ETM59E-04 Application Manual Real Time Clock Module RX8804 CE Preliminary
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ETM59E Revision History Rev No. ETM59E-01 ETM59E-02 Date Page 16.Apr.2018 18.Apr.2018 Release 4 Updated Pull-up Resistor value. 35 Updated mention of tCD. 40 EVIN connects to VDD of 32kHz-TCXO. 5 4 ETM59E-03 27.Apr.2018 10 11 41 16 ETM59E-04 Description 14.Jun.2018 40 Note of Timing chart. I2C bus time out is 1second(Max,) from 2seconds, Peak Current consumption (2) 50µA(Typ.) from 55µA(Typ.) 8.2.5. Extension register The default value was updated. 8.2.6.
RX8804 CE Table of Contents 1. Overview...................................................................................................................................................... 1 2. Block Diagram ............................................................................................................................................. 1 3. Terminal description ....................................................................................................................................
RX8804 CE I2C-Bus Interface Real-time Clock Module RX8804 CE Features built-in 32.768 kHz DTCXO. 2 Supports I C-Bus's high speed mode (Up to 400 kHz) Time -Stamp function with EVIN-Pin trigger. Outputs to SOUT-Pin of each of detection Flag or others. Alarm interrupt function for day, date, hour, and minute settings Fixed-cycle timer interrupt function Time update interrupt function Temperature compensated 32.
RX8804 CE 3. Terminal description 3.1. Terminal connections RX8804CE 1. FOE 10. / INT 2. VDD 9. GND 3. EVIN 8. T2 4. FOUT 7. SDA 5. SCL 6. SOUT 3.2. Pin Functions Signal name I/O Function SDA I/O This pin's signal is used for input and output of address, data, and ACK bits, synchronized 2 with the serial clock used for I C communications. Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable pull-up resistance relative to the signal line capacity.
RX8804 CE 4. Absolute Maximum Ratings GND=0V Item Symbol Condition Rating Unit Supply voltage VDD Between VDD and GND 0.3 to +6.5 V Input voltage (1) VIN1 FOE, SCL, SDA, EVIN pins ND0.3 to +6.5 V Input voltage (2) VIN2 EVIN pin GND0.3 to VDD+0.3 V Output voltage (1) VOUT1 FOUT and SOUT pin GND0.3 to VDD+0.3 V Output voltage (2) VOUT2 SDA and /INT pins GND0.3 to +6.5 V Storage temperature TSTG When stored separately, without packaging 55 to +125 C 5.
RX8804 CE 7. Electrical Characteristics 7.1. DC Characteristics *Unless otherwise specified, GND=0V,VDD=1.5Vto5.
RX8804 CE 7.2. AC characteristics * Unless otherwise specified, GND=0V,VDD= 1.6Vto5.5V,Ta=40Cto+105C Item Symbol Condition SCL = 100 kHz (Standard-Mode Min. Max. SCL = 400 kHz (Fast-Mode) Min. Max. Unit fSCL 100 400 kHz Start condition setup time tSU;STA 4.7 0.6 µs Start condition hold time tHD;STA 4.0 0.
RX8804 CE 8. Use Methods 8.1. Description of Registers 8.1.1. Write/Read and Bank Select Address 00h to 0Fh: Basic time and calendar register. It compatible with RX-8803 and RX8900 Address 10h to 1Fh: Extension register Access to more than address 20h is possible, but there is some control register for quality inspection. When more than Address auto increment is looping in lower 4 bits address. Upper 4bits address are fixed. (00, ..., 0E, 0F, 00, 01) (10, ...
RX8804 CE 8.1.3.
RX8804 CE 8.2. Details of Registers 8.2.1. Clock counter (SEC - HOUR) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 SEC 40 20 10 8 4 2 1 01 MIN 40 20 10 8 4 2 1 02 HOUR 20 10 8 4 2 1 “o” indicates write-protected bits. A zero is always read from these bits. The clock counter counts seconds, minutes, and hours. The data format is BCD format. For example, when the “seconds” register value is “0101 1001” it indicates 59 seconds.
RX8804 CE 8.2.2. Calendar counter (WEEK - YEAR) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 1 0 WEEK 6 5 4 3 “o” indicates write-protected bits. A zero is always read from these bits. 03 1) Day of the WEEK counter The day (of the week) is indicated by 7 bits, bit 0 to bit 6. The day data values are counted as follows: Day 01hDay 02hDay 04hDay 08hDay 10hDay 20hDay 40hDay 01hDay 02h, etc.
RX8804 CE 8.2.3. Alarm registers Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 08 09 MIN Alarm HOUR Alarm WEEK Alarm DAY Alarm AE AE 40 6 20 20 5 20 10 10 4 10 8 8 3 8 4 4 2 4 2 2 1 2 1 1 0 1 0A AE The alarm interrupt function is used, along with the AEI, AF, and WADA bits, to set alarms for specified date, day, hour, and minute values.
RX8804 CE 3) USEL (Update Interrupt Select) bit This bit is used to define if the RTC should output a “second update” or “minute update” interrupt, allowing to synchronize external clocks with the time registers of the RTC. USEL Data Write/Read Auto reset time tRTN update interrupts 0 second update 1 minute update Default 500 ms Min. 7.813 ms 4) TE (Timer Enable) bit This bit controls the start/stop setting for the fixed-cycle timer interrupt function.
RX8804 CE 4) VLF (Voltage Low Flag) bit This flag bit indicates the retained status of clock operations or internal data. Its value change from “0” to “1” indicates a possible data loss or time data error due to a supply voltage drop. Once this flag bit's value is “1”, its value is retained until a “0” is written to it. After powering up from 0 V, make sure to set this bit's value to “1”. Please confirm table in 8.11. Backup and Recovery.
RX8804 CE 8.2.7. Control register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 0F Control Register CSEL1 CSEL0 UIE TIE AIE (Default) (0) (1) (0) (0) (0) 1. 2. bit 2 bit 1 bit 0 RESET (0) (0) (0) The default value is the value that is read (or is set internally) after powering up from 0 V. “o” indicates write-protected bits. A zero is always read from these bits.
RX8804 CE 4) AIE (Alarm Interrupt Enable) bit When an alarm timer interrupt event occurs (when the AF bit value changes from “0” to “1”), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a “1”is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated.
RX8804 CE 8.3. Fixed-cycle Timer Interrupt Function The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.14µs and 32 years. When an interrupt event is generated, the /INT pin goes to low level and “1” is set to the TF bit to report that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin occurs only when the value of the control register's TIE bit is “1”.
RX8804 CE 8.3.2. Related registers for function of fixed-cycle timer interruption The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.14 s and 16777215 minutes.
RX8804 CE 2) TSTP (Timer STOP) bit This bit controls the temporarily stopped of Timer Counter. TSTP Data Write/Read 0 1 Description Timer Counter are stopped. (don’t reset.) Count down of the Timer Counter are continued. 3) TRES (Timer Reset) bit This bit can be employed like Watch Dog Timer function. TRES Data Write/Read 0 1 Description The Timer Counter is not affected. Preset value are loaded to all Timer Counters.
RX8804 CE 8.3.3. Fixed-cycle timer interrupt interval (example) Source clock Preset Value 0 1 2 4096 Hz 64 Hz "Second" update "Minute" update TSEL1,0 = 0,0 TSEL1,0 = 0,1 TSEL1,0 = 1,0 TSEL1,0 = 1,1 244.14 s 488.28 s 15.625 ms 31.25 ms 41 82 128 192 205 320 410 640 820 1229 1280 1920 2048 2560 3200 3840 4095 10.010 ms 20.020 ms 31.250 ms 46.875 ms 50.049 ms 78.125 ms 100.10 ms 156.25 ms 200.20 ms 300.05 ms 312.50 ms 468.75 ms 500.00 ms 625.00 ms 0.7813 s 0.9375 s 0.
RX8804 CE 8.4. EVIN Interrupt and Time stamp Function 8.4.1. Diagram of EVIN interrupt function "1" "1" (4) EIE bit "0" (5) Hi-z (7) /INT output "L" (6) "1" (3) (2) EF bit "0" (1) Event occurs RTC internal operation Write operation (1) The EVIN interrupt event occurred. (2) At the same time, EF bit values becomes “1”. (3) When the EF bit = “1”, its value is retained until it is cleared to zero.
RX8804 CE 8.4.2. Operation example of Time-Stamp function. 125 ms Over 1μsec EVIN EF INT When EIE or EF is cleared to 0, INT is released to Hi-Z immediately. EIE 1 Command example STEP 5 234 contents Supplement Disabled Time-stamp function. Low-active is specified. Enables Pull-Up resistor. Disabled repeat detection. Disable interruption of EVIN detection. Debounce period is 125ms Disable interruption of Time update, Timer and Alarm. In first, disabled interruption of Event trigger input.
RX8804 CE 1) Time stamp Seconds data from Year data. When detect trigger input from EVIN terminal, Clock and calendar data are recorded. 2) TSVLF, TSVDET bit TSVLF bit copies from VLF bit. TSVDET bit copies from VDET bit. 3) ECP (Event capture Enable) bit ECP enables Time Stamp function. ECP Data Write/Read Function 0 Time-stamp is disabled. 1 Time-stamp is enabled. Time-stamp data are overwritten by latest time-stamp data.
RX8804 CE 7) EIE (EVIN Interrupt Enable) bit When valid event input occurs (when the EIF bit value changes from “0” to “1”), this bit's value specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated. (/INT status remains Hi-Z). EIE Data Description 0 1) When a EVIN interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status remains Hi-Z).
RX8804 CE 8.5. SOUT Interrupt Function Controller can select and use interrupt of a voltage drop or other detection of RTC, as a hardware interruption, and controller can use SOUT like as GPO port. 8.5.1. Operation example of SOUT function. VDD 1.45V (Typ.) VDET flag SOUT Hi-Z Hi-Z 123 4 5 6 (7,8,9) Hi-Z A B C D E (Ex.1) When a VDD voltage fell, SOUT outputs active LOW signal.
RX8804 CE 8.5.2. Related registers for SOUT interrupt functions. Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 19 SOUT Enable SOE7 SOE6 SOE5 SOE4 SOE3 SOE2 SOE1 SOE0 1A SOUT Select DCE DC - - SRV FS2 FS1 FS0 1) SOE0 to SOE7 (SOUT Enable) bits When value of address 0x19 is 0x69, SOUT pin output function is enabled. When value of address 0x19 is other value, SOUT pin are disabled.
RX8804 CE 8.6. Time Update Interrupt Function The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event occurs, the UF bit value becomes “1” and the /INT pin goes to low level to indicate that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INTpin occurs only when the value of the control register's UIE bit is “1”.
RX8804 CE 8.6.2. Related registers for time update interrupt functions. Address Function bit 7 bit 6 bit 5 bit 4 USEL 0D Extension Register TF UF 0E Flag Register CSEL1 CSEL0 TIE UIE 0F Control Register )o indicates write-protected bits. A zero is always read from these bits.
RX8804 CE 8.7. Alarm Interrupt Function The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to “1” and the /INT pin goes to low level to indicate that an event has occurred. Example of /INT operation AIE ="1" ( AF="0""1" ) AF="1""0"or AIE="1""0" 8.7.1.
RX8804 CE 8.7.2.
RX8804 CE 3) AF (Alarm Flag) bit When this flag bit value is already set to “0”, occurrence of an alarm interrupt event changes it to “1”. When this flag bit value is “1”, its value is retained until a “0” is written to it. AF Data Description 0 Write The AF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero enables /INT low output to be canceled (/INT remains Hi-Z) when an alarm interrupt event has occurred.
RX8804 CE 8.8. About the interrupt function for operation /INT = “L” interrupt output. 1) How to identify events when the interrupt output occurred? /INT output pin is common output terminal of interrupt events of three types (Fixed-cycle timer Time interrupt, alarm interrupt, time update interrupt). When an interrupt occurs, please read the TF, AF, UF flag to confirm which types of events occurred. 2) Processing method when not using an interrupt output. 1. Please keep interrupt pin not connected. 2.
RX8804 CE 8.10. Reading/Writing Data via the I2C Bus Interface 8.10.1. Overview of I2C-BUS 2 The I C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data transfer signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed.
RX8804 CE 2 8.10.3. Starting and stopping I C bus communications START Repeated START(RESTART) condition condition STOP condition SCL [S] [ Sr ] [P] SDA 1s ( Max. ) 1) START condition, repeated START condition, and STOP condition (1) START condition The SDA level changes from high to low while SCL is at high level. (2) STOP condition This condition regulates how communications on the I2C-BUS are terminated. The SDA level changes from low to high while SCL is at high level.
RX8804 CE 2 8.10.4. Data transfers and acknowledge responses during I C-BUS communications 1) Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no longer than 1 second.) Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
RX8804 CE 2 8.10.6. I C bus protocol In the following sequence descriptions, it is assumed that the CPU is the master and the RX8804 is the slave. a. Address specification write sequence Since the RX8804 includes an address auto increment function, once the initial address has been specified, the RX8804 increments (by one byte) the receive address each time data is transferred. (1) CPU transfers start condition [S]. (2) CPU transmits the RX8804's slave address with the R/W bit set to write mode.
RX8804 CE 8.11. Backup and Recovery This circuit is sensitive to power supply noise and supply voltage should be stabilized to avoid negative impact on the accuracy. tR1 is needed for a proper power-on reset. If this power-on condition cannot be kept, it is necessary to send an initialization routine to the RTC by software. In case of repeated ON/OFF of the power supply within short term, it is possible that the power-on reset becomes unstable.
RX8804 CE 8.12. About access at the time of backup return and initial power supply Because most of RTC registers are synchronized with the oscillation clock of the built-in crystal oscillator, the RTC does not work normally without the integrated oscillator having stabilized. Please initialize the RTC at the time the power supply voltage returns (VLF = 1) after the oscillation has stabilized (after oscillation start time tSTA).
RX8804 CE 8.13. Flow chart The following flow-chart is one example, but it is not necessarily applicable for every use-case and not necessarily the most effective process for individual applications. 1) An example of the initialization Ex.1 Initialize Initialization Reg0Dh Set TE bit to “0”. Set FSEL1,0 bitoptionally. Reg0Dh SET TEST bit to “0”. Clear VDET, VLF bit to “0”. Set AIE,TIE, UIE bit to “0"to prevent unprepared interruption output.
RX8804 CE 2) Method of initialization after starting of internal oscillation (VLF stays “0”) power on Wait time of 30 ms is necessary at least Wait VLF=1 ? NO Whether it is a return from the state of the backup is confirmed. YES When an internal oscillation starts, 0 writing of VLF is approved.
RX8804 CE 3) The setting of the clock and calendar Set time Set RESET bit to “1” to prevent timer update in time setting. RESET"1" Write time Write information of[year/month/date[day of the week]hour: minute: second] which is necessary to set (or reset). In case of initialization, please initialize all data. Please complete access within 0.95 seconds Next process 4) The reading of the clock and calendar Reading of the clock Read clock Please complete access within 0.
RX8804 CE 8.14. Connection with Typical Microcontroller VDD VDD SCL 2 I C-BUS Master SDA INT EVIN VDD SCL FOUT FOE RX8804 SLAVE ADRS = 0110 010 R/W VDD SDA SOUT GND Pull up Registor R= tr C BUS SCL SDA ( I2C Bus ) 8.15. When used as a clock source (32 kHz-TCXO) RX8804 VDD T2 VDD SCL SDA 32.768kHz 0.
RX8804 CE 9. External Dimensions/Marking Layout 9.1. RX8804CE 9.1.1. External dimensions External dimensions Recommended soldering pattern 3.2 ± 0.2 1.1 0.2 Min. 1.0 Max. 2.5 ± 0.2 0.9 0.3 0.4 0.35 0.4 0.3 0.62 0.7 0.7 0.42 The small metal pads on the short side of the ceramic package are used to test the crystal. When assembling the part, please be careful not to connect or short circuit this pads.
RX8804 CE 10. Application notes 1) Notes on handling This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling. (1) Static electricity While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials.
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