Installation Guide

C5621 and C33 User Guide
1/1553-KRD 131 24 Uen Rev D 2011-11-22

Ericsson AB 2011
13 (37)
Ericsson Confidential
If solder mask is used on the mother PCB underneath the C5621/C33, it
should be NSMD design with SMO of Ø ≥0.73 mm.
Figure 2, Ø 0.63 mm NSMD solder lands, SMO Ø ≥0.73 mm
4.2 Digital I/O routing
 Keep all trace lengths as short as possible
 Use stripline structure for signals with high frequency content (on the
module, all 1.8V I/O signals have a rise/fall time of ~1ns, and should
therefore be routed as striplines, since they all are high bandwidth
signals)
 Treat all critical (high bandwidth) signals as current loops, and make
sure that they have a return path. This means that you should refrain
from routing any signals over non-continuous power or ground planes,
because this causes interruptions in the impedance and results in
reflections, and might also increase EMI emissions.
 Traces routed on adjacent layers should be oriented perpendicular
towards each other; this will reduce risk for crosstalk.
 Impedance matching must be maintained to avoid overshoot,
undershoot and ringing. Otherwise, radiated emissions increases.
 If nothing else is stated, digital signals should be routed with an
impedance of 50-70 Ohm relative GND.
NSMD Solder lands
Host PCB Solder Mask