Data Sheet

Beijing Eswin Technology Co.,Ltd
2.3.1 Watchdog Timers
The watchdog timer provides a two-stage mechanism to prevent a system from
lock-up. The first stage is called “interrupt stage”. If the watchdog interrupt is
enabled and the watchdog timer is not restarted during the interrupt stage, the
interrupt signal, wdt_int , will be asserted. The second stage, reset stage,
begins right after the interrupt stage. If the watchdog reset is enabled and the
watchdog timer is not restarted during the reset stage, the reset signal, wdt_rst ,
will be asserted.
2.4 System Clocks
2.4.1 CPU Clock
Upon reset, an external crystal clock source 40MHz is selected as the default
CPU clock. The external crystal clock source also connects to a PLL to
generate a high frequency clock (typically 160 MHz).Depending on the
application the CPU clock frequency can auto switch in 160MHz,80
MHz,40MHz and 32KHz.
2.4.2 RTC Clock
The RTC clock from internal RC oscillator (typically about 32.75 KHz).The
internal RC clock can be calibration by the 40MHz from the external crystal.
2.5 Radio
The TR6260 radio consists of the following main blocks:
• 2.4 GHz receiver
• 2.4 GHz transmitter
• bias and regulators
• balun and transmit-receive switch
• clock generator