Model 5100S/5500S Service Manual Mainboard D/D board Inverter board Hard transfer board Specifications are subject to change without notice.
Contents System specifications ........................................................................................... 1 Chipsets ................................................................................................................ 3 SiS630S ................................................................................................................. 3 PC Card Chipset ..................................................................................................... 8 CPU and Memory ...
Battery Pack .......................................................................................................... 41 Battery diagram ..................................................................................................... 44 Component diagrams and part numbers ........................................................... 45 Schematic Drawings ...........................................................................................
System specifications The 5100S/5500S uses the SiS630S core logic and InSyde BIOS code. This product also features three bays for user-installed modules (a HDD, a CD-ROM or DVD-ROM or a FDD), and has an optional Fax/Modem MDC module.
Keyboard Power Saving Management Keys Fn key support 84 YES Doze mode Sleep mode YES YES Integrated numeric keypad Inverted "T" layout cursor keys YES YES Suspend/Resume mode Suspend to HDD mode YES YES Hot key control suspend APM ver 1.2 support YES YES ACPI Ver 1.0 support YES TouchPad built-in Interface x1 PS/2 Power Supply AC adapter AC-in Capacity LCD TFT/DSTN 100-240V 47-63Hz 65W Battery pack Li-Ion Physical Dimension Weight 316mm(W) 256mm(D) Backlite Size CCFT 12.
Chipsets SiS630S – provides a high performance/low cost Desktop solution for the Intel mobile CPU – based system integrates a high performance North Bridge – has an advanced hardware 2D/3D GUI engine, Super-South bridge or an external AGP4X Slot The SiS630S is a system-on-chip solution that complies with – – Easy PC Initiative which supports Instantly Available/OnNow PC technology USB – – Legacy Removal Slotless Design and FlexATX form factor The SiS630S: – – integrates UltraAGPTM technology and
Host Interface Controller - Supports Intel mobile Pentium II/!!! CPUs Synchronous Host/DRAM Clock Scheme - Asynchronous Host/DRAM Clock Scheme Integrated DRAM Controller - 3-DIMM/6-Bank of 3.
Fast PCI IDE Master/Slave Controller - Supports PCI Bus Mastering Native Mode and Compatibility Mode - PIO Mode 0, 1, 2 , 3, 4 Multiword DMA Mode 0, 1, 2 - Ultra DMA 33/66/100 Two Independent IDE Channels Each with 16 DW FIFO Virtual PCI-to-PCI Bridge Integrated Ultra AGP VGA for Hardware 2D/3D Video/Graphics Accelerators - Supports Tightly Coupled 64 Bits Host Interface to VGA to Speed Up GUI Performance and Video Playback Frame Rate - AGP v. 2.
- Built-in VESA Plug and Display for CH7003, PanelLinkTM and LVDS Digital - Interface Built-in Secondary CRT Controller for Independent Secondary CRT, LCD or TV - digital output Supports VESA Standard Super High Resolution Graphic Modes 640x480 800x600 16/256/32K/64K/16M colors 120 Hz NI 16/256/32K/64K/16M colors 120 Hz NI 1024x768 1280x1024 256/32K/64K/16M colors 120 Hz NI 256/32K/64K/16M colors 85 Hz NI 1600x1200 1920x1440 256/32K/64K/16M colors 85 Hz NI 8bbp/16bbp 60NI - Low Resolution Modes
- Serial IRQ - Interrupt Sources Re-routable to Any IRQ Channel Three 8254 Compatible Programmable 16-bit Counters - System Timer Interrupt Generate Refresh Request - Speaker Tone Output Integrated Keyboard Controller - Hardwired Logic Provides Instant Response Supports PS/2 Mouse Interface - Password Security and Password Power-Up System Sleep and Power-Up by Hot-Key - KBC and PS2 Mouse Can Be Individually Disabled Integrated Real Time Clock (RTC) with 256B CMOS SRAM - Supports ACPI Day-of-M
PC Card Chipset The PCI1410 supports the following features: - Ability to wake from D3 hot and D3 cold Fully compatible with the IntelE 430TX (Mobile Triton II) chipset A 144-Pin Low-Profile QFP (PGE), 144-ball MicroStar Ball Grid Array (GGU) package, or 209-ball MicroStar Ball Grid Array (GHK) package - 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments - Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.
CPU and Memory CPU The 5100S/5500S Notebook PC uses the Intel Mobile Pentium III/Celeron (.18) processor in a µPGA2 package. The Intel Mobile Pentium III/Celeron (.18) processor features an integrated L2 cache(256KB for Pentium III and 128KB for Celeron (.18)) and a 64-bit high performance system bus. The Mobile Pentium III/Celeron (.
Adding or replacing the processor. Note: If you plan on removing the heat sink, which is necessary to add or replace the processor, you will need to have a replacement heat sink pad available. Before proceeding, please contact your dealer to get a replacement pad which you will need when you reinstall the heat sink.
B: Remove the processor The processor is secured on the mainboard with a lock which is easily opened using a small regular screwdriver. With the heat sink already removed you will need to set the lock to the open position before removing the processor: processor mounted on the socket O L Processor socket Lock OPEN 1) Turn the screw on the processor lock to the open position.
O 2) Lift the processor from the socket. L C: Insert a new processor 1) With the processor lock in the open position, align the pins of the processor with the holes in the socket. O 2) Press the processor into the socket.
D: Reinstall the heat sink Note: When reinstalling the heat sink, you will also have to replace the heat sink pad. A heat sink pad can be obtained from your dealer. 1) Peel off the old heat sink pad and stick on a new one. 2) Insert the heat sink cable in the slot. (Figure 4-3) 3) Align the 4 screw holes on the heat sink with those on the mainboard and screw them in about half way. Once all the screws are in about half way and the heat sink is seated probably tighten the screws.
4) Remove the metal protective shield 5) Locate the SW DIP Switch on the right side. 6) Change the settings to the following: SW settings for Intel Speedstep processor SW1-1 SW1-2 SW1-3 SW1-4 ON ON ON OFF 7) Put the metal shield back into place 8) Put the keyboard back into place.
Memory The computer has two memory sockets for PC-100/PC-133 compliant, 144 pin SODIMM (Small Outline Dual In-line Memory Module) modules. The memory can be expanded to 512 MB with the following combinations: Bank 0 (64-bit) Bank 1 (64-bit) 32 MB 32 MB 64 MB 64 MB 64 MB 128 MB 128 MB 128 MB 128 MB 256 MB 256 MB 256 MB 256 MB 256 MB Empty 32 MB Empty 32 MB 64 MB Empty 32 MB 64 MB 128 MB Empty 32 MB 64 MB 128 MB 256 MB Power 3.
Expansion Memory Socket The Model 5100S/5500S Notebook PC has two 144-pin SODIMM type memory sockets with the following configuration: Pin SDRAM Pin SDRAM Pin SDRAM Pin SDRAM 1 Vss 2 Vss 73 Reserved 74 CLK1 3 DQ0 4 DQ32 75 Vss 76 Vss 5 DQ1 6 DQ33 77 Reserved 78 Reserved 7 DQ2 8 DQ34 79 Reserved 80 Reserved 9 DQ3 10 DQ35 81 Vdd 82 Vdd 11 Vdd 12 Vdd 83 DQ16 84 DQ48 13 DQ4 14 DQ36 85 DQ17 86 DQ49 15 DQ5 16 DQ37 87 DQ18 88 DQ50 17 DQ6 18
Installing a Memory Module 1) Turn off the computer. 2) Press the two keyboard latches at the top of the keyboard to elevate the keyboard from its normal position. 3) Carefully lift the keyboard assembly out to expose the mainboard. Figure 4-1 Bank 1 Bank 0 4) Locate the memory banks, Bank 0 is on the right and Bank 1 is on the left. Figure 4-2 Note: Only use Bank 0 if you have one memory module. If you are using two memory modules always use the larger module in Bank 0.
Note: Make sure the connectors go into the bank. You must use a RAM module that complies with Intel unbuffered SODIMM (67.6 mm x 29.0 mm). Please consult your dealer for the details. 67.6 mm 29.0 mm connectors Changing the S3 DIP Switch settings Once you have installed the new memory you will have to change the DIP Switch settings depending on the type of memory you have installed.
Removing a Memory Module 1) Turn off the computer. 2) Press the two keyboard latches to elevate the keyboard from its normal position (refer to Figure 4-1) 3) Carefully lift the keyboard assembly out to expose the mainboard. 4) Locate the memory sockets. Bank 0 is on the left and Bank 1 is on the right. (refer to Figure 4-2) 5) Gently pull the two latches outward on both ends of the module 6) The module will pop up . . 7) Remove the memory module .
Drive information and Pin assignments Storage Devices HDD (BUILT-IN) - 2.5", 12.7mm max.
Removing the HDD from the notebook 1) Turn the computer off. 2) Turn the computer over. 3) Locate the HDD latch . 4) Slide and hold the latch forward then slide the HDD out of the computer. 5) Lift the hard disk drive out of the computer. Removing the HDD from its tray 1) Remove the HDD case from the computer (refer to Removing the HDD in Chapter 2 for details). 2) Remove the two sets of screws on the side of the case. 3) Slowly remove the HDD from the case until you see the connecting cable.
FDD - 3.5", 1.44MB floppy disk drive 3-Mode support for Japanese market FDD PIN ASSIGNMENT Pin Description Pin Description 1 +5 V 2 INDEX 3 +5 V 4 DRIVE SELECT0 5 +5 V 6 DISK CHANGE 7 N.C. 8 Ready 9 HD(High : HD) 10 MOTOR ON 11 N.C.
8) Remove the two screws on each side of the FDD tray. 9) Remove the FDD from its tray. (see picture) fastening screws fastening screws The FDD floppy disk drive out of its bay Inserting the Floppy Disk Drive Follow the instructions for removing the FDD in reverse order.
DVD-ROM - Model Matsushita SR8173 Dimensions 128mm(W)x12.
Removing the DVD-ROM Module Removing the DVD-ROM Module 1) Turn off the computer. 2) Turn the computer over. 3) Locate the DVD/FDD cover . 4) Unscrew and remove the cover. 5) Remove the single screw which holds the DVD-ROM in the computer . 6) Locate the cable tab and gently pull the cable tab upward to disconnect the DVD-ROM from the computer mainboard .
CD-ROM (OPTIONAL) - Model Dimensions Matsushita CR175 128mm(W)x12.
Interface Pin Assignments RS-232 Serial Interface The RS-232C Serial Interface uses a 9 pin D-sub male connector with the following configuration: Pin 1 2 3 4 5 6 7 8 9 Description DCD (DATA Carrier Detect) RXD (Received Data) TXD (Transmitted Data) DTR (Data Terminal Ready) GND (Signal Ground) DSR (Data Set Ready) RTS (Request To Send) CTS (Clear To Send) RI (Ring Indicator) Parallel Interface The Parallel interface uses a 25-pin D-sub female connector with the following configuration: Pin 1 3 5 7 9 11
Internal trackpad Interface The internal trackpad interface connector has the following configuration: Pin 1 2 3 4 5 6 7 8 9 Description EKDA EMDA GND VCC EKCLK EMCLK GND GND GND External Monitor Interface The external monitor interface uses a 15-pin D-sub female connector with the following configuration: Pin 1 2 3 4 5 Description RED GREEN BLUE NC GND Pin 6 7 8 9 10 Description GND GND GND NC GND Pin 11 12 13 14 15 Description NC DDCDA HSYNC VSYNC DDCLK RGB Out: - Output Impedance : 75 Ohms RGB
PCMCIA CardBus Interface Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A35 A36 A37 A38 A39 Description CardBus 16Bit Card GND GND GND GND A_CAD0 A_D3 A_CCD1# A_CD1# A_CAD14 A_D4 A_CAD2 A_D11 A_CAD3 A_D5 A_CAD4 A_D12 GND GND A_CAD5 A_D6 A_CAD6 A_D13 A_CAD7 A_D7 RFU A_D14 A_CC/BE0# A_CE1# A_CAD9 A_D15 A_CAD10 GND A_CAD9 A_A10 A_CAD10 A_CE2# A_CAD11 A_OE# A_CVS1 A_VS1# A_CAD12 A_A11 GND GND A_CAD13 A_IORD# A_CAD14 A_A9 A_CAD15 A
Internal PCI Interface (For optional modem or LAN card) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 Description GND GND GND AUXBR AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 CBE#1 PAR VCC SERR# PERR# STOP# DEVSEL# TRDY# IRDY# FRAME# CBE#2 GND VCC3 VCC3 VCC3 GND GND VCC VCC VCC AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 3
LCD Interface ( For XGA TFT) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 Description INVVCC ENABL GND FLM GND CONTADJ PANELID0 GND LCDVDD TXOUTV0GND TXOUTV1+ TXOUTV2GND TXCLKV+ Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 31 Description INVVCC BRIGADJ LP DISPOFF# CL2 LDE PANELID1 LCDVDD GND TXOUTV0+ TXOUTV1GND TXOUTV2+ TXCLKVGND
Power Application: This specification shall apply to the power module to be operated in the Notebook 5100S/ 5500S system. The power board provides the following voltages for Intel P!!! CPUs: 1.35V &1.6V for CPU VCC_CORE Input Power: a. Adapter: +20.0V Constant Voltage Mode (65W ). b. Battery: LI-ION Smart Battery ( 47.36W ). c.
Output Protection Requirements: a. Over current protection: Vcc OCP —7A max Vcc3 OCP — 7A max Vcc_Core OCP — 20A max VccT OCP — 3.5A max Vcc1.8 OCP — 3.5A max b. Output Short Protection : Vcc,Vcc3,12V,Vcc_Core,VccT,Vcc1.8 The power supply shall not be damaged by short form the output to return . Battery Protection: The discharge circuits should be SHUTDOWN when the voltage for the Li-ion battery voltage is down to 12V(+/-0.
Interface Specifications JP1. Battery Connector (Off The Mother Board) PIN 1~8 9 SIGNAL B+ BAT-DATA 10 11 12 13~20 TEMP BAT-CLK CELL GND CNA1. DC/DC Connector (Off The Power Board) PIN 1~6 7 8~13 14 ~ 21 22~27 28~33 34~39 40~42 SIGNAL B+ VR_ON GND VCC3 GND VCC GND 12V CN4.
Charge board Battery parameters The BIOS will download all battery parameters to the smart charger before POST. The battery parameters are as follows: LI-ION CHG V LI-ION DESINH V (0x39) : Li-ion CV = (0x39) /3 *4 (0x3A) : ERROR = (0X3A) * 1.27 +2.3V LI-ION EDVI LI-ION EDVF (0x3B) : EDVI = (0x3B) /3 *4 (0x3C) : EDVI = (0x3C) /3 *4 Default EDVI and EDVF and Constant Voltage: Battery Item Voltage LI-ION Constant Voltage 16.8V ± 0.2V EDVI 11.4V ± 0.2V EDVF 10.8V ± 0.
Hardware ShutDown: Battery Type Max Voltage LI-ION 12V ± 0.2V Max Voltage Protection : Battery Type Max Voltage LI-ION 17.1V ± 0.2V O.P.T ( Protect for environment temperature ) : For a LI-ION battery charger start, if the temperature exceeds 50°C or falls below 5°C, the charger shall not charge and the charge indicator will show no charger current. If the environment temperature is below 50°C the charger shall auto reCharge.
Alert : The charge controller will send an alert signal, when the adapter is plugged in or out, when the battery is inserted or removed, or when the battery is low. During the alert signal, the charge controller will send the low signal pulse three times within a 10 second period. Battery low alarm : When the battery is low, the charge controller will send out the battery low alert. If KBC or the OS doesn’t respond, the battery will go to the low signal in 2 seconds.
Inverter board APPLICATION : This specification refers to an inverter which operates a cold cathode fluorescent lamp for a liquid-crystal display module. This inverter is designed for the 12.1” TFT LCD-modules. ELECTRICAL CHARACTERISTICS: ITEM Input Voltage Input Current Inrush Current Lamp Current Output Voltage Frequencey Starting Voltage BKLO BRIGADJ MIN 4.5 5.5 2.5 1000 0 0 TYPE 5 900 6.0 3.0 560 60 - MAX 5.5 4 6.5 3.5 3.3 2.
Adapter Configuration : 3-wire input AC line (line, neutral, FG) Input characteristics: Input Voltage: 100 ~ 240 +10%vac,Full range Input Frequency: 47 ~ 63 Hz Input Current : 1.6A max @115VAC,at full load. 0.8A max @230VAC,at full load. Efficiency: 80 % (min) .at full load . Output characteristics: Output power: 65W (max) Output Current: ITEM TOLERANCE OUTPUT CURRENT Output voltage (Accuracy) Min Max +20Vdc (main) +/- 5% 0 3.
Over Current Protection : The power supply will not be damaged by an over current from the output (measure at 110 Vac input). OUTPUT VOLTAGE LOWER UPPER +20 to 10.0 Vdc 3.3A 3.8A Short circuit protection: A short circuit place at any output will cause no damage. ESD requirements : The adapter shall withstand IEC PUB. 801-5 (surge ) level 4 requirements. EMI / EMC : The radiated and conducted emissions of this AC adapter complies with the requirements of the FCC PART 15, CLASS B & EN55022.
Battery Pack Recharging by AC Power The battery pack automatically recharges when it is installed into a computer that is connected to an AC power supply. You can still use the computer when it is recharging. To fully recharge the battery will take several hours and may be slightly longer if the computer is being used while the battery is recharging. Proper Handling of the Battery Pack DO NOT disassemble the battery pack under any circumstances.
1. 2. Completely recharge the battery. Use the battery until it is fully discharged 3. Recharge the battery to 100% capacity. (In this case it doesn’t matter whether or not the computer is being used) Note: An empty battery will become damaged if stored too long and by following these steps the battery cycle life and the battery life will increase.
Removing the battery pack 1) Turn the computer over. 2) Slide the latch in the direction indicated . 3) Gently grasp the battery pack on the edge below the latches and lift it out of the bay . Inserting the battery pack 1) Turn the computer over. 2) Place the battery in its bay inserting the side without the latch in first. 3) Push down on the side with the latch until it clicks into place.
Battery diagram 44
Component diagrams and part numbers 10 6 8 1 2 13 4 11 4 5 3 7 9 21 17 15 25 22 12 23 14 20 4 31 19 16 22 22 22 18 7 33 22 34 29 35 36 22 28 22 24 26 14 7 30 31 32 45
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4 6 5 3 13 11 7 16 14 9 15 15 12 2 8 1 15 10 ITEM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PART NAM E DISPLAY FRONT PANEL LCD 12.1" TFT SANYO TM 121SV-02L07 DISPLAY BACK PANEL HOOK KNOW HOOK SPRING FOR HOOK EXTEN INVERTER LCD BRACKET (L) LCD BRACKET (R) CA BLE 1H/2H 28AW G 35P 203m m DISPLAY RUBBER PAD DISPLAY RUBBER PAD SCREW SCREW SCREW SCREW PART NO.
48
1 22 6 2 7 3 5 21 9 2 3 8 10 5 9 15 2 11 16 8 17 12 4 19 10 7 13 2 14 15 16 17 20 18 2 49
50
VC C T R 1 91 H8 H 10 H 12 H 14 H 16 J7 J9 J 11 J 13 J 15 K8 K 10 K 12 K 14 K 16 L7 L9 L 11 L 13 L 15 M 8 M 10 M 12 M 14 M 16 N7 N9 N 11 N 13 N 15 P8 P 10 P 12 P 14 P 16 R7 R9 R 11 R 13 R 15 T8 T 10 T 12 T 14 T 16 U7 U9 U 11 U 13 U 15 U4 BP R I# 3 BP R I# A6 C PU R ST# 3 C PU R ST# R S#0 U1 3 R S#0 A A2 R S#1 3 R S#1 W1 R S#2 3 R S#2 Y1 Z1 T U2 H TR D Y # 3 H T R D Y# D E FE R # U3 3 D E F ER # R 2 44 1 1 0 _ 1 %ED G E C T R L P A A 1 6 1 1 ,1 2 ,2 0 C PU _ S T P# 12 A 20 M # 1 2 IG N N E# 1 2 IN IT # 1
52 .1U .1U 4.
VCCT M DD[ 0. . 63] R1 3 2 C1 5 5 7 5_1% .001 U C3 8 1 R3 9 7 5 6 . 2 _1 % 1 RS # 2 1 RS # 1 1 RS # 0 .1 U 1 V 29 T 29 R 26 P 25 G 27 R 29 G 28 RS#2 RS#1 RS#0 V 26 R 25 U 29 HIT M# HI T # DRDY # DBS Y # BNR# U 26 R 24 U 28 T 27 U 27 P 28 HREQ#4 HREQ#3 HREQ#2 HREQ#1 HREQ#0 R 27 T 26 T 28 R 28 P 27 ADS# ADS# 1 HI T M # 1 H IT # 1 DR DY # 1 DB S Y # 1 B NR # VS SQA VS SQB 53 HA # [ 3.. 3 1 ] 1 HA#[ 3. .
V CC3 3 MA A13 3 MA A11 3 MA A10 3 MA A9 3 MA A3 3 MA A6 3 MA A8 3 MA A12 1 2 3 4 MA A13 MA A11 MA A10 MA A9 1 2 3 4 MA A3 MA A6 MA A8 MA A12 1 2 3 4 8 7 6 5 RN45 RN36 8P 4R -10 8P 4R -10 8 7 6 5 8 7 6 5 RN35 8P 4R -10 RN34 8P 4R -10 8 7 6 5 IMA B1 IMA B2 IMA B0 IMA B4 IMA B1 IMA B2 IMA B0 IMA B4 Z45 IMA B5 IMA B7 IMA B14 T IMA B5 5 IMA B7 5 IMA B14 5 IMA B13 IMA B11 IMA B10 IMA B9 IMA B3 IMA B6 IMA B8 IMA B12 5 5 5 5 MDD[ 0..
V CC 3 MEM_V CC L2 1 J 32 1 6H S4 8 0 C9 0 C8 8 C8 7 10U 10U .1U BBAANNKK00 MEM_V CC MD [0 ..6 3] MD [0 ..6 3] 4 MD [0 ..6 3] BBAANNKK11 MEM_V CC MEM_V CC MD [0 ..
V CC 3 9 R ED RED R3 42 0 Z6 31 C 9 H SY NC 9 V SY NC T 11 V OS CI R3 69 C1 50 14 0 _1 % B 14 A 14 A 15 HSY NC V SY NC D 15 A 16 C 15 B 16 S SY NC C 16 VO SCI A 11 RSET E 19 630VREF .1U C3 27 Z6 31 Z6 32 Z6 33 DDCDA DDCLK 9 D DC DA 9 DD CLK 1U COMP C 14 B 15 DA CA VD DC F 18 56 B K2 1 2 5H S3 30 C3 29 C3 28 4 .7U T T T T ROUT GOUT B OUT H SY NC V SY NC 4 .
V CC 3 V CC 3 +12 V R6 1 6 C6 9 C6 3 5 4.7U .1U R6 2 0 R6 3 8 V CC 3 U9 1 D 2 D 3 G 1M R6 3 7 Z29 4 10K E NA V DD # R6 3 9 6,8 E NA V DD # 0 D S 0 E NA B K K L E NAB L E NAB L 6 D Q7 8 S 2N 700 2 LC DV DD 5 4 C6 3 4 C6 2 6 C7 4 .1U 4.7U 6 EN A BK KL # EN A BK KL # 8 D IS P OFF # D IS P OFF # G FOR DS TN .
V CC 3 12 L_ T XD 1 7 L_ T XD 1 4 L_ T XD 0 12 L_ T XD 0 16 V CC C5 5 0 6 M I1D I0D YD 9 L_ T XD 2 12 L_ T XD 2 E# YC YB I1C I0C I1B I0B YA V CC I1A I0A 13 14 L_ R XE E R 92 11 S DO L_ R XE E R 13 10 11 L_ T X DD 2 92 11 S CS L_ T X DD 2 13 6 5 L_ T X DD 1 92 1 1 S D IN L_ T X DD 1 13 3 2 L_ T X DD 0 9 211 S CL K L_ T X DD 0 13 5P 6 P [ 0.. 17] DOT CLK 6 D OT CL K 6 V B H SY NC 6 V B V SY NC P [ 0..
1 4,2 3 IDEA VDD AD[ 0.. 31] A D[0 ..3 1 ] R 496 0 V C C1 .8 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C 448 C 449 C 453 .00 1 U .1 U 4 .7 U C1 C2 C3 PG NT #2 PG NT #1 PG NT #0 D2 D3 D4 C/ BE#3 C/ BE#2 C/ BE#1 C/ BE#0 F3 H4 J1 L1 INT #A INT #B INT #C INT #D N1 P4 P5 P3 PG NT #[ 0. . 2] 1 4 P GN T # [0..2 ] 1 4,2 3 P REQ#2 P REQ#1 P REQ#0 C/ BE#[ 0. . 3] C /B E # [0..
8 ,9 ,1 3, 14,1 6,21 ,2 3 PC I RS T # PC I RS T # C8 9 9 9 9 9 DD P 6 DD P 7 DD P 8 DD P 9 9 DD P 4 9 DD P 5 9 D D P1 0 9 D D P1 1 P DD P 2 P DD P 3 PD D P 1 2 PD D P 1 3 P DD P 0 P DD P 1 PD D P 1 4 PD D P 1 5 RN9 8 7 6 5 DD P 6 DD P 7 DD P 8 DD P 9 8 7 6 5 DD P 4 DD P 5 D D P1 0 D D P1 1 P DD P 2 P DD P 3 PD D P 1 2 PD D P 1 3 R N1 0 R N1 1 1 2 3 4 P DD P 0 P DD P 1 PD D P 1 4 PD D P 1 5 1 2 3 4 R N1 2 9 ID E -I R Q1 4 9 P IO R DY 9 PD R E Q ID E -I R Q1 4 R 53 1 8P 4R -1 0 1 2 3 4 1 2
' ƒ‡„s ¥ a“æC L OC K GENER A TOR IC U22 1 15 19 27 30 36 42 C LKVC C L23 CLKVCC VC C3 B K2125H S330 6 C103 C443 C442 C109 C110 C126 C127 C125 C119 C118 C135 C108 .1U 10U .001U .1U .001U .1U .001U .1U .001U .1U 3 16 22 33 39 .001U 470P 10 VD D VD D VD D VD D VD D VD D L27 47 CLKVCC2.5 B K2125H S330 C441 C438 C106 C107 C436 C437 C439 C440 .1U .001U 10U .1U C104 .001U .1U 22P .001U 470P 4 14XIN-1 Y2 VD DPCI GNDR EF GN D GN D GN D GN D FS 3/R EF0 R EF1 C PU2.5_3.
VC C 3 V VD D 3 8 7 6 5 VC C 3 R 475 R 485 R 484 4 .7 K 4 .7 K 4 .7 K 8 P 4 R - 4 .
LRX+ L RX + R6 01 5 6.2 _1 % Transformer C5 64 .1 U Z660 C5 73 R6 05 5 6.2 _1 % C LRX- LRX - C6 23 C Z1 44 T Z1 45 1 2 3 4 L 80 RX + RX RX C 16 15 14 RD+ RD RDC NC 13 NC T PLACE NEAR THE TRANSFORMER 7 8 6 LT X+ LT X- LT X+ LT X - R6 35 R6 36 6 1.9 _1 % T Z1 46 5 T X+ TX T XC T D+ TDT DC NC NC Z1 56 10 9 11 Z1 49 12 Z1 50 T D+ T D- C6 22 .
V CC 3 R 5 57 0 (12 06 ) R 5 58 3 1 0K (R) PME# 1 9 P ME # 4 1 C 5 35 IN OU T IN OU T EN OU T GN D OC # R 5 59 B _ V CC_ C V C C 3_ A U X U 13 2 8 7 6 5 V C C3 _ A U X B_VCC _C C 5 34 1 2 3 4 .1 U Z 1 74 T C 5 07 C 5 37 C 5 39 C 5 08 C 4 94 C 4 93 C 5 09 C 5 36 C 4 97 C 4 92 C 5 17 C 4 98 .1 U .1 U .01 U .01 U .01 U .01 U .1 U .1 U .1 U .1 U 4 .7 U 4 .7 U 1 2 3 4 T P S 2 0 32 (R) .
VCC3 C278 U39 4 5 6 7 8 CV ID0 CV ID1 CV ID2 CV ID3 CV ID4 CV ID0 CV ID1 CV ID2 CV ID3 CV ID4 11,23 SCL_A T FF 11,23 SDA_A T FF SCL_A T FF SDA_A T FF 1 2 12 VR_H I/LO# VR_H I/LO# 16 R265 18 10 1K (R) Z178 S CL SD A OV ER RID E # LEV E L N ON_MUX_OU T WP GN D AS E L 9 +12V U14 12V BV C C BV C C BV C C C86 15 14 13 12 11 Y0 Y1 Y2 Y3 Y4 MUX_S E L .
83 626 CLK 1 1 83 626 CLK C2 6 V CC V CC R U6 13 14 21 22 23 19 18 17 16 LF RAM E# PCI RST # 1 2 LFR A ME # 8,9,10,13 ,1 4 ,2 1,2 3 P CIR ST # 1 1 83 626 CLK 1 2 LD R EQ # 12 ,1 4,1 7 SIRQ 1 2 L AD 0 1 2 L AD 1 1 2 L AD 2 1 2 L AD 3 83 626 CLK LDREQ # SIRQ LAD0 LAD1 LAD2 LAD3 5 45 55 70 85 10 5 12 0 20 25 V CC C2 4 C6 5 C4 5 C4 6 10U .1 U .1 U .1 U V CC 3 R6 6 8 C2 5 4 .
FIRVCC L85 VCC3 F IR 4 3 2 1 4 3 2 1 BK2125HS330 R5 4.7K 47K 5 6 7 8 R2 RN70 8P4R-18 5 6 7 8 RN71 8P4R-18 3 IRTX2 9 U1 RXD LEAD 8 FIR_SEL MDO T XD 11 MD1 GNDPAD NC R6 4.7K 4 Z2 01 R3 2.2K 5 Z2 02 R4 2.2K FIRGND VCC IRTX2 IRRX2 IRR3 AGNDD IRR3 GND IRRX2 10 Z2 03 VCC3 JA1 2 1 2 7 6 HSDL -36 00 1 C5 Z667 SHORT -A .1 U C659 .0 47 U C660 10U T FIRGND 16,19 7,16,19 SA[0..1 5] SA[0..
V CC C58 1 28 Z213 24 Z214 1 C59 2 .1 U_ K % 1 7 S O UT 1 1 7 RT S 1 # 1 7 DT R1 # 2 0 COM1RI 1 7 DS R1 # 1 7 R I1 # 1 7 CT S 1 # 1 7 S IN 1 1 7 DC D1 # Z215 2 S O UT 1 RT S 1 # DT R1 # 14 13 12 COM1RI DS R1 # R I1 # CT S 1 # S IN 1 DC D1 # 20 19 18 17 16 15 23 V CC R61 5 10 0K T Z224 Z223 22 21 C1 + C1- V CC Z212 C59 1 .1 U_ K % 26 .1U U4 7 V+ V- 27 Z217 3 Z216 C58 3 C2 + .1 U_ K % C58 2 .
L4 6 C3 1 7 V CC C OL 8 C OL 7 C OL 6 C OL 5 C OL 4 C OL 3 C OL 2 C OL 1 R OW 1 R OW 2 A R OW 6 A E MCLK EMDA D4 4 C R OW 4 R OW 4 EK DA E K CLK 1S S35 5 D4 3 A C 1S S35 5 D4 1 R OW 7 R OW 5 R OW 9 R OW 1 0 R OW 1 1 R OW 8 R OW 1 2 R OW 3 R OW 1 6 R OW 1 3 R OW 1 4 R OW 1 5 S R3 1 1 D 0 PW R_ ON # 10 9 8 7 6 10 9 8 7 6 C OL 4 C OL 3 C OL 2 C OL 1 G 7 8 68P 68P 68P K B_ ON # 12 22 V CC A D4 6 C1 7 1 C3 1 1 C3 1 2 4.7U .1U .
D 25 R2 18 HD _L E D 10 HD _L E D A Z280 33 0(0 80 5) C S ML _0 10 MT _ G D 24 VC C C6 29 .1 U VC C 16 ME MW # 1 FL A S H # U 48 IN 2 ME MW # 5 VC C R6 47 10 K IN 3 Z258 C 4 GN D OU T T C 7S H 3 2F U D 68 22 24 1 31 B IOS CS # ME MR # 16 B IOS CS # 16 ME MR # Z259 A W BIOS # CE OE VP P PGM 1S S3 5 5 C 73 13 14 15 17 18 19 20 21 O0 O1 O2 O3 O4 O5 O6 O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 S A [0..
C 54 TP 8 T T T T T P1 74 T P1 76 T P 4 .01 U(R) C ID 0 C ID 1 NC G ND NC G ND NC NC G ND G ND st atus MAST ER SLA VE SLA VE SLA VE L 10 Z300 T T T P 1 7T7P 1 7 5 Z307 R 35 R 36 R 42 C ID 0 C ID 1 L 75 V CC 3 Z317 C 43 20 K (R) 20 K (R) R 1 V D DA O UT .01 U C 36 C 37 .1U 4 .7 U C6 5 4 C6 5 3 4 .7 U .1U .01 U 1 9 25 38 AGND 2 A UD CLK 3 Z6 81 C 71 Z6 54 5 R Z6 55 Z6 56 6 8 10 11 .
T T P 96 P W RS W # S D 2 N7 00 2 (R ) S4 R 7 38 0 Z7 2 9 5 3 Z 354 H CH _ 5 1 _ P W R _ BU T T O N 7 C 2 60 12 63 0 P W R S W # 63 0 P W R S W # R 2 1 3 Q .1 U (R ) 1 C 2 K B _ O N# C D 22 A K B _ S US# D 20 A F 01 J 2 E (R ) K B _ O N# 19 P W R _ON C 2 71 R 2 50 10 K (R ) R 2 12 10 K (R ) A Z 356 D D B+ R 5 12 L T 11 21 .1 U _K % (1 2 0 6 ) .1 U _K % (1 2 0 6 ) A DA P C 4 57 R 5 11 C 4 56 4 .7U 1 00 K (R ) G 2 N 70 02 .
V CC 3 V CC 3 V CC 3 AD[0. . 31] V CC AD0 AD2 AD4 AD6 AD8 AD10 AD12 AD14 9,14 9,14 9,14 9,14 C/ BE#0 C/ BE#1 C/ BE#2 C/ BE#3 C /B E #0 C /B E #1 C /B E #2 C /B E #3 V CC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 K1 L L L L L L L L L L L L L L L L U U U U U U U U U U U U U U U U 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 AD1 AD3 AD5 AD7 AD9 AD11 AD13 AD15 8 7 6 5 AD[0. . 31] R5 47 R5 46 1K 1K RN 6 R6 70 R6 71 R5 81 R5 80 C6 89 8P 4R -4 .
D D 74 A F5 B+ 5A C Z401 C2 75 0.1U F(0805) C2 38 22UF/25V(DIP 10X5) 5 Z4 03 Q 46 2 N39 06 5 4 C2 94 Q 29 S I4884 (S O8) V CC _CO RE 4 1 2 3 2 D 16 A R2 55 200K (0603) VC C2_ CO RE + N8 N9 N 10 N 11 N 12 C Z402 1 2 3 R2 56 10K Q 28 S I4884 (S O8) 6 7 8 12 G CL _GA T E R 6 7 8 11,27 VR _ON 10K R2 76 V CC 3 R2 63 F1 J4 C C2 86 IN T V CC R2 95 1 0.1U F L 53 1.5uH (MOD IN G) Z4 16 R1 73 14m (1206) C2 92 C2 06 C2 04 47U F/6.3V(D) 47U F/6.3V(D) C2 07 C2 09 C2 91 47U F/6.
P3 C417 0.1UF R461 4.7 Z425 U23 R 2 EXT VCC RUN/SS INT VCC + VIN C142 22UF/25V(C) P3 4 B+ + C687 16 Z422 TG 5A 100UF/25V(6.3X7)-L D5 F1J4 15 BOOST L36 Z423 R89 14m(1206) N1 1 COSC 14 SW C430 0.22UF 5 Q17 SI4416(SO-8) C Z419 6 7 8 C Z418 9 4.7UF(1206)5 F2 Q16 SI4416(SO-8) 1 2 3 R482 12 Z671 A 13 C428 6 7 8 Z688 SDS1005-4R7M N2 D57 33PF Z424 Z420 12,19,22,23,28,29 PWR_ON R435 10K Z460 Q67 2N3906 4 R460 11 Z426 BG F1AJ3 4 ZD2 2.
FA 1 7A Z 433 B -1 C A 12 IN T V C C -1 C A 10 1 2V -1 C A 33 4 .7U F/3 5 V (12 0 6)(R ) R A 27 5 R 1(0 8 05 ) 0 .1U F /5 0V (1 2 06 ) V CC3-1 C A 15 0 .1 U F(0 8 05 ) + Z 554 A DA4 C A 19 4 .7U F/3 5 V (12 0 6)(R ) CA2 C 100UF /25V (6.3 x 7) 2 2 U F /2 5 V (D IP 1 0X 5 ) F1 J4 C A 23 2 .
V D D 1 .8_ B + C6 6 4 Z7 2 3 C Z6 9 2 C D7 1 D A V D D 1 .8 + N1 3 R3 4 3 7 6 4 C6 6 6 5 C FB 1 2 Z6 9 8 5V SD # C6 6 7 C6 6 5 V D D 1 .8 VO VO GND 3 VI ERR OR # 8 U4 9 M A C A -2 9 5 1 (S O -8 ) 4 3 .2 K / F C6 8 8 D7 5 2 .4 V 2 . 2 U F /2 5 V (1 2 0 6 ) .1 U R6 8 9 2 . 2 U F /2 5 V (1 2 0 6 ) 1K V CC 3 Z 45 9 R3 4 5 N1 4 N1 5 10 0K/F 4 . 7 U F /6 .
C R 1 27 R 1 21 0 1 00 K R 1 20 R R 3 50 R 15 R 3 72 R R 3 62 R 1 29 10K 10K R 1 25 C 1 58 1 0U F (12 0 6) 10K 28 Z4 69 9 Z4 70 C 3 66 0 .1U F C 3 44 1U F /16 V (08 0 5) 10 Z4 71 16 R 1 30 R 1 26 R R P B 1/T C A P P A 0 /P W M0 P A 1 /P W M1 P A 2 /P W M2 P A 3 /P W M3 P A 4 /S C L0 P A 5 /S D A 0 P A 6 /S C L1 P A 7 /S D A 1 V dd 1UF /16V (0805) 7 H i => R es et C h arg er R 1 19 R 3 59 R 3 71 R R 4.7K 4.
F1 A DA PT E R 5A Z 63 0 L2 9 6 00 (1 2 06 ) Z 49 5 6 00 (1 2 06 ) C 13 0 10 P (1 2 06 ) Z 64 9 C 12 9 C 12 2 1 00 0 P L3 0 0 .1U /50 V (1 2 06 ) D12 K S 8 23 C 0 4 (T O -2 52 ) A1 C VA R 10 3 100m (2512) VC B+ A2 Z 495 VC C 34 5 0 .
