Datasheet

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74AC08, 74ACT08 — Quad 2-Input AND Gate

74AC08, 74ACT08 Rev. 1.5.1

January 2008

74AC08, 74ACT08

Quad 2-Input AND Gate

Features

■

reduced by 50% on 74AC only

■

Outputs source/sink 24mA

General Description

The AC08/ACT08 contains four, 2-input AND gates.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Connection Diagram

Pin Description

Logic Symbol

IEEE/IEC

Order

Number

Package

Number Package Description

74AC08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74AC08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74AC08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74ACT08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74ACT08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Names Description

, B

Inputs

Outputs

Summary of content (10 pages)

PAGE 1
74AC08, 74ACT08 Quad 2-Input AND Gate Features General Description ■ ICC reduced by 50% on 74AC only The AC08/ACT08 contains four, 2-input AND gates. ■ Outputs source/sink 24mA Ordering Information Order Number Package Number Package Description 74AC08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.
PAGE 2
Symbol VCC IIK Parameter Rating Supply Voltage –0.5V to +7.0V DC Input Diode Current VI = –0.5V –20mA VI = VCC + 0.5 +20mA VI DC Input Voltage –0.5V to VCC + 0.5V IOK DC Output Diode Current VO = –0.5V –20mA VO = VCC + 0.5V +20mA VO DC Output Voltage –0.5V to VCC + 0.
PAGE 3
Symbol VIH Parameter VCC (V) Minimum HIGH Level Input Voltage 3.0 Maximum LOW Level Input Voltage 3.0 Minimum HIGH Level Output Voltage 3.0 TA = +25°C Conditions VOUT = 0.1V or VCC – 0.1V Units 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 1.5 0.9 0.9 2.25 1.35 1.35 2.75 1.65 1.65 2.99 2.9 2.9 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 2.56 2.46 3.86 3.76 4.86 4.76 0.002 0.1 0.1 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 0.36 0.44 0.36 0.44 0.36 0.44 ±0.1 ±1.0 µA 4.
PAGE 4
Symbol VIH VIL VOH Parameter VCC (V) Conditions Typ. TA = –40°C to +85°C Guaranteed Limits VOUT = 0.1V or VCC – 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT = 0.1V or VCC – 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = –50µA 4.49 4.4 4.4 Minimum HIGH Level Input Voltage 5.5 Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage TA = +25°C 4.5 4.5 5.5 4.5 5.49 VIN = VIL or VIH, 5.4 5.4 3.86 3.76 4.86 4.76 0.1 0.1 Units V V V IOH = –24mA 5.
PAGE 5
TA = +25°C, CL = 50pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay TA = –40°C to +85°C, CL = 50pF VCC (V)(6) Min. Typ. Max. Min. Max. Units 3.3 1.5 7.5 9.5 1.0 10.0 ns 5.0 1.5 5.5 7.5 1.0 8.5 3.3 1.5 7.0 8.5 1.0 9.0 5.0 1.5 5.5 7.0 1.0 7.5 ns Note: 6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. AC Electrical Characteristics for ACT TA = +25°C, CL = 50pF Symbol Parameter TA = –40°C to +85°C, CL = 50pF VCC (V)(7) Min. Typ.
PAGE 6
8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.
PAGE 7
4AC08, 74ACT08 — Quad 2-Input AND Gate Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
74AC08, 74ACT08 — Quad 2-Input AND Gate Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3.
PAGE 9
74AC08, 74ACT08 — Quad 2-Input AND Gate Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4.
PAGE 10
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