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74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input

74AC14, 74ACT14 • Rev. 1.7.2

February 2011

74AC14, 74ACT14

Hex Inverter with Schmitt Trigger Input

Features

■ I

reduced by 50%

■ Outputs source/sink 24mA

■ 74ACT14 has TTL-compatible inputs

General Description

The 74AC14 and 74ACT14 contain six inverter gates

each with a Schmitt trigger input. They are capable of

transforming slowly changing input signals into sharply

defined, jitter-free output signals. In addition, they have a

greater noise margin than conventional inverters.

The 74AC14 and 74ACT14 have hysteresis between the

positive-going and negative-going input thresholds (typi-

cally 1.0V) which is determined internally by transistor

ratios and is essentially insensitive to temperature and

supply voltage variations.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Order

Number

Package

Number Package Description

74AC14SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74AC14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACT14SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74ACT14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Summary of content (10 pages)

PAGE 1
74AC14, 74ACT14 Hex Inverter with Schmitt Trigger Input Features General Description ■ ICC reduced by 50% The 74AC14 and 74ACT14 contain six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional inverters.
PAGE 2
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names Description In Inputs On Outputs ©1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 • Rev. 1.7.2 Function Table Input Output A O L H H L www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Parameter Rating Supply Voltage –0.5V to +7.0V DC Input Diode Current VI  –0.5V –20mA VI  VCC + 1.
PAGE 4
TA  +25°C VCC Symbol VOH Parameter (V) Minimum HIGH Level 3.0 Output Voltage 4.5 Conditions IOUT  –50µA 5.5 VOL IIN(3) Vt+ Vt– VH(MAX) Maximum LOW Level Output Voltage ICC 2.9 4.49 4.4 4.4 5.4 5.4 2.56 2.46 4.5 IOH  24mA 3.86 3.76 5.5 IOH  24mA 4.86 4.76 3.0 IOUT  50µA (1) 0.002 0.1 0.1 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 0.36 0.44 Units V V 3.0 IOL  12mA 4.5 IOL  24mA 0.36 0.44 5.5 IOL  24mA(1) 0.36 0.44 Maximum Input Leakage Current 5.
PAGE 5
VCC (V) Symbol Parameter VIH Minimum HIGH Level Input Voltage 4.5 Maximum LOW Level Input Voltage 4.5 Minimum HIGH Level Output Voltage VIL VOH TA  +25°C Conditions Typ. TA  –40°C to +85°C Guaranteed Limits VOUT  0.1V or VCC – 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT  0.1V or VCC – 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT  –50µA 4.49 4.34 4.4 5.49 5.4 5.4 3.86 3.76 4.86 4.76 0.1 0.1 5.5 5.5 4.5 VIN  VIL or VIH, Units V V V IOH  –24mA 5.
PAGE 6
TA  +25°C, CL  50pF Symbol tPLH tPHL Parameter TA  –40°C to +85°C, CL  50pF VCC (V)(6) Min. Typ. Max. Min. Max. Units 3.3 1.5 9.5 13.5 1.5 15.0 ns 5.0 1.5 7.0 10.0 1.5 11.0 3.3 1.5 7.5 11.5 1.5 13.0 5.0 1.5 6.0 8.5 1.5 9.5 Propagation Delay Propagation Delay ns Note: 6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. AC Electrical Characteristics for ACT TA  +25°C, CL  50pF Symbol Parameter TA  –40°C to +85°C, CL  50pF VCC (V)(7) Min.
PAGE 7
8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 (0.33) 1.75 MAX 1.50 1.25 1.27 LAND PATTERN RECOMMENDATION M C B A SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.
PAGE 8
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 9
0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.
PAGE 10
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input ©1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 • Rev. 1.7.2 www.fairchildsemi.