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74LCX07 — Low Voltage Hex Buffer with Open Drain Outputs

74LCX07 Rev. 1.11.1

74LCX07

Low Voltage Hex Buffer with Open Drain Outputs

Features

■

5V tolerant inputs

■

2.3V to 5.5V V

specifications provided

■

2.9ns t

max. (V

3.3V), 10µA I

max.

■

Power down high impedance inputs and outputs

■

+24mA output drive (V

3.0V)

■

Latch-up performance exceeds JEDEC 78 conditions

■

ESD performance:

– Human body model

2000V

– Machine model

200V

■

Leadless DQFN package

General Description

The LCX07 contains six buffers. The inputs tolerate volt-

ages up to 7V allowing the interface of 5V systems to 3V

systems.

The outputs of the LCX07 are open drain and can be

connected to other open drain outputs to implement

active HIGH wire AND or active LOW wire OR functions.

The 74LCX07 is fabricated with advanced CMOS tech-

nology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Ordering Information

Note:

1. DQFN package available in Tape and Reel only.

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LCX07M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX07SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX07BQX

(1)

MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74LCX07MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Implements p

roprietary

noise/EMI reduction circuitry

December 2013

Summary of content (12 pages)

PAGE 1
74LCX07 Low Voltage Hex Buffer with Open Drain Outputs Features General Description ■ 5V tolerant inputs The LCX07 contains six buffers. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. ■ 2.3V to 5.5V VCC specifications provided ■ 2.9ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high impedance inputs and outputs ■ +24mA output drive (VCC = 3.
PAGE 2
74LCX07 — Low Voltage Hex Buffer with Open Drain Outputs Connection Diagram Logic Symbol Pin Assignments for SOIC, SOP, and TSSOP IEEE/IEC Pad Assignments for DQFN (Top Through View) (Bottom View) Pin Description Pin Names Description An Inputs On Outputs DAP No Connect Note: DAP (Die Attach Pad) ©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.1 www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VI Parameter Rating Supply Voltage –0.5V to +7.0V DC Input Voltage –0.5V to +7.
PAGE 4
TA = –40°C to +85°C Symbol VIH VIL Parameter VCC (V) HIGH Level Input Voltage LOW Level Input Voltage Conditions Min. Max. 2.3–2.7 1.7 2.7–3.6 2.0 4.5–5.5 0.7 x VCC V 2.3–2.7 0.7 2.7–3.6 0.8 4.5–5.5 VOL II LOW Level Output Voltage IOFF Power-Off Leakage Current ICC Quiescent Supply Current ∆ICC Increase in ICC per Input IOHZ Off State Current V 0.3 x VCC IOL = 100µA 0.2 2.3 IOL = 8mA 0.6 2.7 IOL = 12mA 0.4 3.0 IOL = 16mA 0.4 3.0 IOL = 24mA 0.55 4.
PAGE 5
TA = 25°C Symbol Parameter VCC (V) VOLP Quiet Output Dynamic Peak VOL 3.3 VOLV Quiet Output Dynamic Valley VOL Conditions Typical Unit CL = 50pF, VIH = 3.3V, VIL = 0V 0.9 V 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.7 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6 V Capacitance Symbol Typical Units Input Capacitance VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.
PAGE 6
74LCX07 — Low Voltage Hex Buffer with Open Drain Outputs AC Loading and Waveforms Test Switch VCC x 2 at VCC = 5.0 ± 0.5V tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V Figure 1. AC Test Circuit (CL includes probe and jig capacitance) 3-STATE Output Low Enable and Disable Times for Logic trise and tfall VCC Symbol 5.0V ± 0.5V 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi VCC / 2 1.5V 1.5V VCC / 2 Vmo VCC / 2 1.5V 1.5V VCC / 2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.3V VOL + 0.
PAGE 7
Tape Format for DQFN Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status BQX Leader (Start End) 125 (Typ.) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typ.) Empty Sealed Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.
PAGE 8
74LCX07 — Low Voltage Hex Buffer with Open Drain Outputs Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS.
PAGE 9
74LCX07 — Low Voltage Hex Buffer with Open Drain Outputs Physical Dimensions (Continued) Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 10
74LCX07 — Low Voltage Hex Buffer with Open Drain Outputs Physical Dimensions (Continued) Figure 5. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 11
0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 6. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.
PAGE 12
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