Datasheet

©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX07 — Low Voltage Hex Buffer with Open Drain Outputs
AC Loading and Waveforms
Figure 1. AC Test Circuit (C
L
includes probe and jig capacitance)
3-STATE Output Low Enable and t
rise
and t
fall
Disable Times for Logic
Figure 2. Waveforms (Input Pulse Characteristics; f =1MHz, t
r
= t
f
= 3ns)
Test Switch
t
PZL
, t
PLZ
V
CC
x 2 at V
CC
= 5.0 ± 0.5V
6V at V
CC
= 3.3 ± 0.3V
V
CC
x 2 at V
CC
= 2.5 ± 0.2V
Symbol
V
CC
5.0V ± 0.5V 3.3V ± 0.3V 2.7V 2.5V ± 0.2V
V
mi
V
CC
/ 2 1.5V 1.5V V
CC
/ 2
V
mo
V
CC
/ 2 1.5V 1.5V V
CC
/ 2
V
x
V
OL
+ 0.3V V
OL
+ 0.3V V
OL
+ 0.3V V
OL
+ 0.15V
V
y
V
OH
– 0.3V V
OH
– 0.3V V
OH
– 0.3V V
OH
– 0.15V
74LCX07 Rev. 1.11.1 6