Datasheet

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February 1994

Revised May 2005

74LCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs

74LCX16245

Low Voltage 16-Bit Bidirectional Transceiver

with 5V Tolerant Inputs and Outputs

General Description

The LCX16245 contains sixteen non-inverting bidirectional

buffers with 3-STATE outputs and is intended for bus ori-

ented applications. The device is designed for low voltage

(2.5V or 3.3V) V

applications with capability of interfac-

ing to a 5V signal environment. The device is byte con-

trolled. Each byte has separate control inputs which could

be shorted together for full 16-bit operation. The T/R

inputs

determine the direction of data flow through the device.

The OE

inputs disable both the A and B ports by placing

them in a high impedance state.

The LCX16245 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■ 5V tolerant inputs and outputs

■ 2.3V–3.6V V

specifications provided

■ 4.5 ns t

max (V

3.3V), 20 A I

max

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ 24 mA output drive (V

3.0V)

■ Uses patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model 2000V

Machine model

200V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to V

through a pull-up resistor: the minimum value or the

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Note 2: Ordering code “G” indicates Trays.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number Package Number Package Description

74LCX16245G

(Note 2)(Note 3)

BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LCX16245MEA

(Note 3)

MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LCX16245MTD

(Note 3)

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Summary of content (9 pages)

PAGE 1
Revised May 2005 74LCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs General Description Features The LCX16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The device is byte controlled.
PAGE 2
74LCX16245 Connection Diagrams Pin Descriptions Pin Names Pin Assignment for SSOP and TSSOP Description OEn Output Enable Input T/Rn Transmit/Receive Input A0–A15 Side A Inputs or 3-STATE Outputs B0–B15 Side B Inputs or 3-STATE Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A B0 NC T/R1 OE1 NC A0 B B2 B1 NC NC A1 A2 C B4 B3 VCC VCC A3 A4 D B6 B5 GND GND A5 A6 E B8 B7 GND GND A7 A8 F B10 B9 GND GND A9 A10 A12 G B12 B11 VCC VCC A11 H
PAGE 3
Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current Value IO DC Output Source/Sink Current ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Conditions 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.
PAGE 4
74LCX16245 DC Electrical Characteristics Symbol (Continued) Parameter VCC Conditions ICC Quiescent Supply Current VI VCC or GND 3.6V d VI, VO d 5.5V (Note 7) 'ICC Increase in ICC per Input VIH VCC 0.6V 40qC to 85qC TA (V) Min Units Max 2.3–3.6 20 2.3–3.6 r20 2.3–3.6 500 PA PA Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA Symbol Parameter VCC CL 40qC to 85qC, RL 3.3V r 0.3V 50 pF VCC 2.7V CL 50 pF 500: VCC CL 2.5V r 0.
PAGE 5
74LCX16245 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay.
PAGE 6
74LCX16245 Schematic Diagram Generic for LCX Family www.fairchildsemi.
PAGE 7
4LCX16245 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 7 www.fairchildsemi.
PAGE 8
74LCX16245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A www.fairchildsemi.
PAGE 9
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.