Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state TSSOP 48

February 1994

Revised May 2005

74LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs

74LCX16373

Low Voltage 16-Bit Transparent Latch

with 5V Tolerant Inputs and Outputs

General Description

The LCX16373 contains sixteen non-inverting latches with

3-STATE outputs and is intended for bus oriented applica-

tions. The device is byte controlled. The flip-flops appear

transparent to the data when the Latch Enable (LE) is

HIGH. When LE is LOW, the data that meets the setup time

is latched. Data appears on the bus when the Output

Enable (OE

) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

The LCX16373 is designed for low voltage (2.5V or 3.3V)

applications with capability of interfacing to a 5V signal

environment.

The LCX16373 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■ 5V tolerant inputs and outputs

■ 2.3V–3.6V V

specifications provided

■ 5.4 ns t

max (V

3.3V), 20 A I

max

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ 24 mA output drive (V

3.0V)

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model 2000V

Machine model

200V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to V

through a pull-up resistor: the minimum value or the

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Note 2: Ordering code “G” indicates Trays.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number Package Number Package Description

74LCX16373G

(Note 2)(Note 3)

BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LCX16373MEA

(Note 3)

MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LCX16373MTD

(Note 3)

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

■ Uses proprietary noise/EMI reduction circuitry

Summary of content (10 pages)

PAGE 1
74LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs General Description Features The LCX16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW.
PAGE 2
74LCX16373 Connection Diagrams Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names Description OEn Output Enable Input (Active LOW) LEn Latch Enable Input I0–I15 Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 LE1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC O
PAGE 3
The LCX16373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its I input changes.
PAGE 4
74LCX16373 Absolute Maximum Ratings(Note 4) Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current Value IO DC Output Source/Sink Current ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.
PAGE 5
Symbol (Continued) Parameter VCC Conditions (V) ICC Quiescent Supply Current VI V CC or GND 3.6V d VI, VO d 5.5V (Note 7) 'ICC Increase in ICC per Input VIH VCC 0.6V TA 40qC to 85qC Min Units Max 2.3 3.6 20 2.3 3.6 r20 2.3 3.6 500 PA PA Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA Symbol Parameter 40qC to 85qC, RL 3.3V r 0.3V VCC CL 50 pF VCC 2.7V CL 50 pF 500: VCC CL 2.5V r 0.
PAGE 6
74LCX16373 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V, and 2.7V VCC x 2 at VCC 2.5 r 0.2V tPZH, tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay.
PAGE 7
4LCX16373 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.
PAGE 8
74LCX16373 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.
PAGE 9
74LCX16373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.
PAGE 10
74LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.