Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Buffer, driver SOIC 20

74LCX240 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

74LCX240 Rev. 1.6.0

January 2008

74LCX240

Low Voltage Octal Buffer/Line Driver with 5V Tolerant

Inputs and Outputs

Features

■

5V tolerant inputs and outputs

■

2.3V–3.6V V

specifications provided

■

6.5ns t

max. (V

3.3V), 10µA I

max.

■

Power-down high impedance inputs and outputs

■

Supports live insertion/withdrawal

(1)

■

±24mA output drive (V

3.0V)

■

Latch-up performance exceeds 500mA

■

ESD performance:

– Human body model

2000V

– Machine model

200V

Note:

1. To ensure the high-impedance state during power up

or down, OE

should be tied to V

through a pull-up

resistor: the minimum value or the resistor is

determined by the current-sourcing capability of the

driver.

General Description

The LCX240 is an inverting octal buffer and line driver

designed to be employed as a memory address driver,

clock driver and bus oriented transmitter or receiver. The

device is designed for low voltage (2.5V or 3.3V) V

applications with capability of interfacing to a 5V signal

environment.

The LCX240 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order

Number

Package

Number Package Description

74LCX240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LCX240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX240MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LCX240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Implements proprietary noise/EMI reduction circuitry

Summary of content (12 pages)

PAGE 1
74LCX240 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Features General Description ■ 5V tolerant inputs and outputs The LCX240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. ■ 2.3V–3.6V VCC specifications provided ■ 6.5ns tPD max. (VCC = 3.
PAGE 2
Logic Diagram Pin Description Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs Truth Tables Inputs Outputs OE1 In (Pins 12, 14, 16, 18) L L H L H L H X Z Inputs Outputs OE2 In (Pins 3, 5, 7, 9) L L H L H L H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance ©1994 Fairchild Semiconductor Corporation 74LCX240 Rev. 1.6.0 www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Rating Supply Voltage –0.5V to +7.0V VI DC Input Voltage –0.5V to +7.
PAGE 4
TA = –40°C to +85°C Symbol VIH VIL VOH VOL II Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current IOFF Power-Off Leakage Current ICC Quiescent Supply Current ∆ICC Increase in ICC per Input VCC (V) Conditions Min. 2.3–2.7 1.7 2.7–3.6 2.0 Max. V 2.3–2.7 0.7 2.7–3.6 0.8 2.3–3.6 IOH = –100µA V VCC – 0.2 2.3 IOH = –8mA 1.8 2.7 IOH = –12mA 2.2 3.0 IOH = –18mA 2.4 IOH = –24mA 2.
PAGE 5
TA = 25°C Symbol Parameter VCC (V) VOLP Quiet Output Dynamic Peak VOL 3.3 VOLV Quiet Output Dynamic Valley VOL Conditions Typical Unit CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6 V Capacitance Symbol Parameter Conditions Typical Units Input Capacitance VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.
PAGE 6
Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND Figure 1. AC Test Circuit (CL includes probe and jig capacitance) Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic trise and tfall VCC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.
PAGE 7
4LCX240 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Schematic Diagram (Generic for LCX Family) ©1994 Fairchild Semiconductor Corporation 74LCX240 Rev. 1.6.0 www.fairchildsemi.
PAGE 8
13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 10 0.51 0.35 PIN ONE INDICATOR 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.
PAGE 9
74LCX240 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 10
74LCX240 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 11
74LCX240 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 6. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 12
ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ Power220® POWEREDGE® Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® Fairc