Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74LCX TSSOP 14

October 1995

Revised February 2005

74LCX38 Low Voltage Quad 2-Input NAND Gate (Open Drain) with 5V Tolerant Inputs

74LCX38

Low Voltage Quad 2-Input NAND Gate (Open Drain)

with 5V Tolerant Inputs

General Description

The LCX38 contains four 2-input open drain NAND gates.

The inputs tolerate voltages up to 7V allowing the interface

of 5V systems to 3V systems.

The 74LCX38 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■ 5V tolerant inputs

■ 2.3V to 3.6V V

specifications provided

■ 5.0 ns t

max (V

3.3V), 10 A I

max

■ Power down high impedance inputs and outputs

■ 24 mA output drive (V

3.0V)

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model

2000V

Machine model 150V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number

Package

Package Description

Number

74LCX38M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX38MX_NL

(Note 1)

M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX38SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX38MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LCX38MTCX_NL

(Note 1)

MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names Description

, B

Inputs

Outputs

■ Implements proprietary noise/EMI reduction circuitry

Summary of content (7 pages)

PAGE 1
74LCX38 Low Voltage Quad 2-Input NAND Gate (Open Drain) with 5V Tolerant Inputs General Description Features The LCX38 contains four 2-input open drain NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. ■ 5V tolerant inputs The 74LCX38 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 2.3V to 3.6V VCC specifications provided ■ 5.0 ns tPD max (VCC 3.
PAGE 2
74LCX38 Absolute Maximum Ratings(Note 2) Symbol Parameter Value VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Sink Current (IOL) ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature 0.5 to 7.0 0.5 to 7.0 0.5 to 7.
PAGE 3
TA Symbol Parameter VCC 40qC to 85qC, RL 3.3V r 0.3V VCC CL 50 pF tPZL Propagation Delay Time tPLZ CL 500 : 2.7V 50 pF VCC CL 2.5V r 0.2V Min Max Min Max Min Max 1.5 5.0 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.5 1.5 6.0 tOSHL Output to Output Skew 1.0 tOSLH (Note 5) 1.0 Units 30 pF ns ns Note 5: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
PAGE 4
74LCX38 AC Loading and Waveforms Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPZL, tPLZ 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Pulse Characteristics; f = 1MHz, tr = tf = 3ns) Symbol www.fairchildsemi.com VCC 3.3V r 0.3V 2.7V 2.5V r 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL 0.3V VOL 0.3V VOL 0.
PAGE 5
74LCX38 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.
PAGE 6
74LCX38 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.
PAGE 7
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.