Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Buffer, driver TSSOP 20

July 2001

Revised March 2005

74LCX760 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs

74LCX760

Low Voltage Buffer/Line Driver

with 5V Tolerant Inputs and Open Drain Outputs

General Description

The LCX760 is the Open Drain version of the LCX244. The

LCX760 contains eight non-inverting buffers with 3-STATE

outputs. The device may be employed as a memory

address driver, clock driver and bus-oriented transmitter/

receiver. The LCX760 is designed for low voltage (2.5V or

3.3V) V

applications with capability of interfacing to a 5V

signal environment.

The LCX760 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■ Open drain version of the LCX244

■ 5V tolerant inputs and outputs

■ 2.3V–3.6V V

specifications provided

■ 8.0 ns t

max (V

3.3V), 10 A I

max

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ 24 mA output drive (V

3.0V)

■ Latch-up conforms to JEDEC JED78

■ ESD performance:

Human body model

2000V

Machine model

200V

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to V

through a pull-up resistor: the minimum value or the

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74LCX760WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LCX760SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX760MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LCX760MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

■ Implements proprietary noise/EMI reduction circuitry

Summary of content (10 pages)

PAGE 1
74LCX760 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs General Description Features The LCX760 is the Open Drain version of the LCX244. The LCX760 contains eight non-inverting buffers with 3-STATE outputs. The device may be employed as a memory address driver, clock driver and bus-oriented transmitter/ receiver. The LCX760 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment.
PAGE 2
74LCX760 Pin Descriptions Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs Truth Tables Inputs OE1 Outputs In (Pins 12, 14, 16, 18) L L L L H H H X Z Inputs Outputs OE2 In L L L L H H H X Z (Pins 3, 5, 7, 9) H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance www.fairchildsemi.
PAGE 3
Symbol Parameter Value VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current Conditions 0.5 to 7.0 0.5 to 7.0 0.5 to 7.
PAGE 4
74LCX760 AC Electrical Characteristics TA Symbol Parameter VCC 40qC to 85qC, RL 500: 3.3V r 0.3V CL 50 pF VCC 2.7V CL 50 pF VCC CL 2.5V r 0.2 Units 30 pF Min Max Min Max Min Max tPZL Propagation Delay 0.5 8.0 0.5 9.0 0.5 10.0 tPLZ Data to Output 0.5 7.0 0.5 8.0 0.5 8.4 tPZL Output Enable Time 0.5 8.0 0.5 9.0 0.5 10.0 ns 0.5 7.0 0.5 8.0 0.5 8.4 ns OEn to Out tPLZ Output Disable Time OEn to Out tOSHL Output to Output Skew 1.0 tOSLH (Note 6) 1.
PAGE 5
74LCX760 AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPZL, tPLZ Switch 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol VCC 3.3V r 0.3V 2.7V 2.5V r 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL 0.3V VOL 0.3V VOL 0.15V Vy VOH 0.3V VOH 0.3V VOH 0.15V 5 www.fairchildsemi.
PAGE 6
74LCX760 Schematic Diagram Generic for LCX Family (output pull-up circuitry is not applicable to open drain versions) FIGURE 3. www.fairchildsemi.
PAGE 7
4LCX760 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 7 www.fairchildsemi.
PAGE 8
74LCX760 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.
PAGE 9
74LCX760 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.
PAGE 10
74LCX760 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.