Datasheet

©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVT573, 74LVTH573 Rev. 1.7.0 2
74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Connection Diagram
Pin Description
Functional Description
The LVT573 and LVTH573 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the D
n
inputs enters the
latches. In this condition the latches are transparent, i.e.,
a latch output will change state each time its D-type input
changes. When LE is LOW, the latches store the infor-
mation that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE
) input. When OE is LOW, the standard out-
puts are in the 2-state mode. When OE
is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Logic Symbols
IEEE/IEC
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH to LOW transition
of Latch Enable
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0
–O
7
3-STATE Latch Outputs
Inputs Outputs
LE OE D
n
O
n
XHX Z
HLL L
HLH H
LLX O
0