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74LVT574, 74LVTH574 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

74LVT574, 74LVTH574 Rev. 1.6.0

January 2008

74LVT574, 74LVTH574

Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Features

■

Input and output interface capability to systems at

5V V

■

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH574),

also available without bushold feature (74LVT574)

■

Live insertion/extraction permitted

■

Power Up/Down high impedance provides glitch-free

bus loading

■

Outputs source/sink –32mA/+64mA

■

Functionally compatible with the 74 series 574

■

Latch-up performance exceeds 500mA

■

ESD performance:

– Human-body model

2000V

– Machine model

200V

– Charged-device model

1000V

General Description

The LVT574 and LVTH574 are high-speed, low-power

octal D-type flip-flop featuring separate D-type inputs for

each flip-flop and 3-STATE outputs for bus-oriented

applications. A buffered Clock (CP) and Output Enable

(OE

) are common to all flip-flops.

The LVTH574 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These octal flip-flops are designed for low-voltage (3.3V)

applications, but with the capability to provide a TTL

interface to a 5V environment. The LVT574 and

LVTH574 are fabricated with an advanced BiCMOS

technology to achieve high speed operation similar to 5V

ABT while maintaining a low power dissipation.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LVT574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVT574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVT574MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LVT574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74LVTH574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVTH574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVTH574MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LVTH574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Summary of content (11 pages)

PAGE 1
74LVT574, 74LVTH574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Features General Description ■ Input and output interface capability to systems at The LVT574 and LVTH574 are high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
PAGE 2
Logic Symbols IEEE/IEC Pin Description Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs Functional Description Truth Table The LVT574 and LVTH574 consist of eight edgetriggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops.
PAGE 3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1999 Fairchild Semiconductor Corporation 74LVT574, 74LVTH574 Rev. 1.6.0 www.fairchildsemi.
PAGE 4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Rating Supply Voltage –0.5V to +4.6V VI DC Input Voltage –0.5V to +7.
PAGE 5
T A = –40°C to +85°C Symbol Parameter VCC (V) 2.7 Conditions II = –18mA VIK Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VO ≤ 0.1V or VO ≥ VCC – 0.1V VOH Output HIGH Voltage 2.7–3.6 IOH = –100µA Output LOW Voltage II(HOLD) II(OD)(3) II Max. Units –1.2 2.0 0.8 VCC – 0.2 3.0 IOH = –32mA 2.0 IOL = 100µA 0.2 IOL = 24mA 0.5 IOL = 16mA 0.4 IOL = 32mA 0.5 IOL = 64mA 0.55 75 VI = 2.0V –75 Bushold Input Minimum Drive 3.
PAGE 6
TA = 25°C Conditions Symbol Parameter VCC (V) CL = 50pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 (8) VOLV Quiet Output Minimum Dynamic VOL 3.3 (8) Min. Typ. Max. Units 0.8 V –0.8 V Notes: 7. Characterized in SOIC package. Guaranteed parameter, but not tested. 8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = –40°C to +85°C CL = 50pF, RL = 500Ω VCC = 3.3V ± 0.3V Symbol Parameter Min.
PAGE 7
13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 10 0.51 0.35 PIN ONE INDICATOR 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.
PAGE 8
74LVT574, 74LVTH574 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 9
74LVT574, 74LVTH574 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Figure 3. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 10
74LVT574, 74LVTH574 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 11
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