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74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

74LVX14 Rev. 1.5.0

February 2008

74LVX14

Low Voltage Hex Inverter with Schmitt Trigger Input

Features

■

Input voltage level translation from 5V to 3V

■

Ideal for low power/low noise 3.3V applications

■

Guaranteed simultaneous switching noise level and

dynamic threshold performance

General Description

The LVX14 contains six inverter gates each with a

Schmitt trigger input. They are capable of transforming

slowly changing input signals into sharply defined, jitter-

free output signals. In addition, they have a greater noise

margin than conventional inverters.

The LVX14 has hysteresis between the positive-going

and negative-going input thresholds (typically 1.0V)

which is determined internally by transistor ratios and is

essentially insensitive to temperature and supply voltage

variations.

The inputs tolerate voltages up to 7V allowing the inter-

face of 5V systems to 3V systems.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order

Number

Package

Number Package Description

74LVX14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LVX14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Summary of content (9 pages)

PAGE 1
74LVX14 Low Voltage Hex Inverter with Schmitt Trigger Input Features General Description ■ Input voltage level translation from 5V to 3V The LVX14 contains six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitterfree output signals. In addition, they have a greater noise margin than conventional inverters. ■ Ideal for low power/low noise 3.
PAGE 2
74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names Description In Inputs On Outputs ©1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 Truth Table Input Output A O L H H L www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Rating Supply Voltage –0.5V to +7.0V IIK DC Input Diode Current, VI = –0.
PAGE 4
TA = –40°C to +85°C TA = +25°C Symbol Parameter VCC Conditions Min. Typ. Min. Vt+ Positive Threshold Vt– Negative Threshold 3.0 0.9 VH Hysteresis 3.0 0.3 VOH HIGH Level Output Voltage 2.0 VIN = VIL or VIH, IOH = –50µA 1.9 2.0 1.9 3.0 VIN = VIL or VIH, IOH = –50µA 2.9 3.0 2.9 VIN = VIL or VIH, IOH = –4mA 2.58 VOL 3.0 Max. LOW Level Output Voltage 2.2 Max. Units 2.2 V 1.2 V 0.9 1.2 0.3 V V 2.48 2.0 VIN = VIL or VIH, IOL = 50µA 0.0 0.1 0.1 3.
PAGE 5
TA = –40°C to +85°C TA = +25°C Symbol tPLH, tPHL Parameter Propagation Delay Time VCC (V) CL (pF) 2.7 3.3 ± 0.3 tOSLH, tOSHL Output to Output Skew(3) 2.7 Min. Typ. Max. Min. Max. Units 15 8.7 16.3 1.0 19.5 ns 50 11.2 19.8 1.0 23.0 15 6.8 10.6 1.0 12.5 50 9.3 14.1 1.0 16.0 50 3.3 1.5 1.5 1.5 1.5 ns Note: 3. Parameter guaranteed by design tOSLH = |tPLHm–tPLHn|, tOSHL = |tPHLm–tPHLn| Capacitance TA = –40°C to +85°C TA = +25°C Symbol Parameter Min. Typ. Max.
PAGE 6
74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS.
PAGE 7
4LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.
PAGE 9
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