Datasheet

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June 2014

74LVX3245 • Rev. 1.0.3

74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs

74LVX3245

8-Bit, Dual-Supply Translating Transceiver with

3-State Outputs

Features

 Bidirectional Interface Between 3 V and 5 V Buses

 Inputs Compatible with TTL Level

 3 V Data Flow at A-Port and 5 V Data Flow at B-

Port

 Outputs Source / Sink: 24 mA

 Guaranteed Simultaneous Switching Noise Level

and Dynamic Threshold Performance

 Implements Proprietary EMI Reduction Circuitry

 Functionally Compatible with the 74 Series 245

Related Resources



AN-5001 — Using Fairchild’s LVX Low-Voltage

Dual-Supply CMOS Translating Transceivers

Description

The 74LVX3245 is a dual-supply, 8-bit translating

transceiver designed to interface between a 3 V bus and

a 5 V bus in a mixed 5 V supply environment. The

Transmit/ Receive (T/¯R

The 74LVX3245 is suitable for mixed-voltage

applications, such as notebook computers using 3.3 V

CPU and 5V peripheral components.

) input determines the direction

of data flow. Transmit (active-HIGH) enables data from

A-ports to B-ports; receive (active-LOW) enables data

from B-ports to A-ports. The output enable input, when

HIGH, disables both A- and B-ports by placing them in a

high-impedance condition. The A-port interfaces with

the 3 V bus; the B-port interfaces with the 5 V bus.

Ordering Information

Part Number

Operating

Temperature Range

Package Packing Method

74LVX3245WM

-40 to +85°C

24-Lead Small-Outline Integrated Circuit

(SOIC), JEDEC MS-013, 0.300" Wide

Tubes

74LVX3245WMX Tape and Reel

74LVX3245QSC

24-Lead Quarter-Size Outline Package

(QSOP), JEDEC MO-137, 0.150" Wide

Tubes

74LVX3245QSCX Tape and Reel

74LVX3245MTC 24-Lead Thin-Shrink Small-Outline

Package (TSSOP), JEDEC MO-153,

4.4 mm Wide

Tubes

74LVX3245MTCX Tape and Reel

Summary of content (11 pages)

PAGE 1
74LVX3245 8-Bit, Dual-Supply Translating Transceiver with 3-State Outputs Features Description    Bidirectional Interface Between 3 V and 5 V Buses   Outputs Source / Sink: 24 mA The 74LVX3245 is a dual-supply, 8-bit translating transceiver designed to interface between a 3 V bus and a 5 V bus in a mixed 5 V supply environment. The Transmit/ Receive (T/R̄ ) input determines the direction of data flow.
PAGE 2
Figure 1. Logic Symbol Pin Configuration Figure 2. Pin Configuration Pin Definitions Pin # Name 1 VCCA Supply Voltage 2 T/R̄ Transmit/Receive Input 3, 4, 5, 6, 7, 8, 9, 10 A0, A1, A2, A3, A4, A5, A6, A7 11, 12, 13 GND 14, 15, 16, 17, 18, 19, 20, 21 B7, B6, B5, B4, B3, B2, B1, B0 22 /OE Output Enable Input 23 NC No Connect 24 VCCB © 1993 Fairchild Semiconductor Corporation 74LVX3245 • Rev. 1.0.
PAGE 3
Figure 3. Table 1. Logic Diagram Truth Table Inputs /OE Outputs T/R̄ L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial © 1993 Fairchild Semiconductor Corporation 74LVX3245 • Rev. 1.0.3 74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs Logic Diagram www.fairchildsemi.
PAGE 4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.5 7.0 V -0.5 VCCA +0.5 V An -0.5 VCCA to +0.5 Bn -0.5 VCCB to +0.
PAGE 5
Symbol VIHA VIHB VILA VILB Parameter Conditions VCCA VCCB (V) (V) TA= -25°C Typ. TA=-40 to+85°C Guaranteed Limits An, T/R̄ , Minimum /OE VOUT ≤ 0.1 V or HIGH Level ≥ VCC - 0.1 V Input Voltage B n 3.6 5.0 2.0 2.0 2.7 5.0 2.0 2.0 3.3 4.5 2.0 2.0 3.3 5.5 2.0 2.0 An, T/R̄ , Minimum /OE VOUT ≤ 0.1 V or LOW Level ≥ VCC - 0.1 V Input Voltage B n 3.6 5.0 0.8 0.8 VOHA Minimum HIGH Level Output Voltage VOHB VOLA Minimum LOW Level Output Voltage VOLB 2.7 5.0 0.8 0.8 3.3 4.5 0.8 0.
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Parameter VOLPA Quiet Output Maximum (2, 3) Dynamic VOL 3.3 5.0 0.8 3.3 5.0 1.5 Quiet Output Minimum (2, 3) Dynamic VOL 3.3 5.0 -0.8 3.3 5.0 -1.2 Minimum HIGH Level Dynamic Input (2, 4) Voltage 3.3 5.0 2.0 3.3 5.0 2.0 Maximum LOW Level Dynamic Input (2, 4) Voltage 3.3 5.0 0.8 3.3 5.0 0.8 VOLPB VOLVA VOLVB VIHDA VIHDB VILDA VILDB Conditions TA=-40 to+85°C VCCA VCCB TA= -25°C (V) (V) Typ. Guaranteed Limits Symbol Units V V V V Notes: 2. Worst-case package. 3.
PAGE 7
Symbol Parameter TA=-40 to +85°C, CL=50 pF, VCCA=2.7 V, VCCB=5.0 V Min. Typ. Max. Min. Max. Min. Max. Propagation Delay A to B 1.0 5.4 8.0 1.0 8.5 1.0 9.0 1.0 5.6 7.5 1.0 8.0 1.0 8.5 Propagation Delay B to A 1.0 5.1 7.5 1.0 8.0 1.0 8.5 1.0 5.7 7.5 1.0 8.0 1.0 8.5 Output Enable Time /OE to B 1.0 4.8 8.0 1.0 8.5 1.0 9.0 1.0 6.3 8.5 1.0 9.0 1.0 9.5 Output Enable Time /OE to A 1.0 6.3 8.5 1.0 9.0 1.0 9.5 1.0 6.8 9.0 1.0 9.5 1.0 10.
PAGE 8
The 74LVX3245 is a dual-supply device capable of bidirectional signal translation. This level shifting ability provides an efficient interface between low-voltage CPU local bus with memory and a standard bus defined by 5 V I/O levels. The device control inputs can be controlled by the low-voltage CPU and core logic or a bus arbitrator with 5 V I/O levels.
PAGE 9
8.74 8.59 0.10 24 13 1 12 1.75 A-B A 24 13 5.60 3.99 3.84 0.10 6 A-B 1 0.20 12 .635 C 0.4 2X 12 TIPS 0.635 B 24X 0.3 LAND PATTERN RECOMMENDATION 0.2 TOP VIEW (0.695) 0.178 C A-B D 0.71 0.61 1.49 1.39 45° 0.203 0.101 1.73 MAX 0.161 0.061 8° 2° END VIEW SIDE VIEW 0.61 0.71 0 MIN GAGE PLANE NOTES : A. THIS PACKAGE CONFORMS TO JEDEC M0-137 VARIATION AE B. ALL DIMENSIONS ARE IN MILLIMETERS C. DRAWING CONFORMS TO ASME Y14.5M-1994 D.
PAGE 10
7.8±0.1 A 0.20 TYP 13 24 13 1 12 B 12 1 (1.45) 3.2 6.4 4.4±0.1 (4.45) 5.9 (7.35) 24 0.65 0.20 C B A 0.10 C 0.65 TYP 0.10 C B Z 12° TOP & BOTTOM R0.09MIN 0°- 8° 0.75 0.45 DATE 10/97. (1.
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