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74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

74LVX74 Rev. 1.4.0

February 2008

74LVX74

Low Voltage Dual D-Type Positive Edge-Triggered

Flip-Flop

Features

■

Input voltage level translation from 5V to 3V

■

Ideal for low power/low noise 3.3V applications

■

Guaranteed simultaneous switching noise level and

dynamic threshold performance

General Description

The LVX74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q

) outputs.

Information at the input is transferred to the outputs on

the positive edge of the clock pulse. After the Clock

Pulse input threshold voltage has been passed, the Data

input is locked out and information present will not be

transferred to the outputs until the next rising edge of the

Clock Pulse input.

Asynchronous Inputs:

■

LOW input to S

(Set) sets Q to HIGH level

■

LOW input to C

(Clear) sets Q to LOW level

■

Clear and Set are independent of clock

■

Simultaneous LOW on C

and S

makes both Q and

HIGH

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order

Number

Package

Number Package Description

74LVX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LVX74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Summary of content (9 pages)

PAGE 1
74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Features General Description ■ Input voltage level translation from 5V to 3V The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse.
PAGE 2
Logic Symbols IEEE/IEC Pin Description Pin Names Description D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs Truth Table (Each Half) Inputs Outputs SD CD CP D Q Q L H X X H L H L X X L H X L L X H H H H H H L H H L L H H H X Q0 Q0 L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Rating Supply Voltage –0.5V to +7.0V IIK DC Input Diode Current, VI = –0.
PAGE 4
TA = +25°C Symbol VIH VIL VOH VOL Parameter VCC Conditions Min. Typ. Max. TA = –40°C to +85°C Min. Max. HIGH Level Input Voltage 2.0 1.5 1.5 3.0 2.0 2.0 3.6 2.4 LOW Level Input Voltage 2.0 0.5 0.5 3.0 0.8 0.8 3.6 0.8 0.8 HIGH Level Output Voltage LOW Level Output Voltage Units V 2.4 2.0 VIN = VIL or VIH, IOH = –50µA 1.9 2.0 1.9 3.0 VIN = VIL or VIH, IOH = –50µA 2.9 3.0 2.9 VIN = VIL or VIH, IOH = –4mA 2.58 V V 2.48 2.0 VIN = VIL or VIH, IOL = 50µA 0.0 0.
PAGE 5
TA = –40°C to +85°C TA = +25°C Symbol Parameter tPLH, tPHL Propagation Delay, CPn to Qn or Qn VCC (V) CL (pF) 2.7 3.3 ± 0.3 tPLH, tPHL Propagation Delay, 2.7 CDn to SDn to Qn or Qn 3.3 ± 0.3 tW tS tH tREC fMAX CPn or CDn or SDn Pulse Width Typ. Max. Min. Max. Units 15 7.3 15 1.0 18.5 ns 50 9.8 18.5 1.0 22 15 5.7 9.7 1.0 11.5 50 8.2 13.2 1.0 15 15 8.4 15.6 1.0 18.5 50 10.9 19.1 1.0 22 15 6.6 10.1 1.0 12 50 9.1 13.6 1.0 15.5 2.7 8.5 10 3.3 ± 0.
PAGE 6
74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS.
PAGE 7
4LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.
PAGE 9
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