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74VHC157 Quad 2-Input Multiplexer

May 2007

74VHC157 Rev. 1.2

74VHC157

Quad 2-Input Multiplexer

Features

■

High Speed: t

4.1ns (Typ.) at V

■

Low power dissipation: I

4µA (Max.) at T

25°C

■

High noise immunity: V

NIH

NIL

28% V

(Min.)

■

Power down protection is provided on all inputs

■

Low noise: V

OLP

0.8V (Max.)

■

Pin and function compatible with 74HC157

General Description

The VHC157 is an advanced high speed CMOS Quad

2-Channel Multiplexer fabricated with silicon gate CMOS

technology. It achieves the high speed operation similar

to equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation.

It consists of four 2-input digital multiplexers with com-

mon select and enable inputs. When the ENABLE

input

is held “H” level, selection of data is inhibited and all the

outputs become “L” level. The SELECT decoding deter-

mines whether the I

or I

inputs get routed to their cor-

responding outputs.

An Input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and on two supply systems such as battery

back up. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number.

Connection Diagram Pin Description

Order Number

Package

Number Package Description

74VHC157M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150”

Narrow

74VHC157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC157MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Pin Names Description

–I

Source 0 Data Inputs

–I

Source 1 Data Inputs

Enable Input

S Select Input

–Z

Outputs

Summary of content (10 pages)

PAGE 1
74VHC157 Quad 2-Input Multiplexer tm Features General Description ■ High Speed: tPD = 4.1ns (Typ.) at VCC = 5V ■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C The VHC157 is an advanced high speed CMOS Quad 2-Channel Multiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.
PAGE 2
Functional Description The VHC157 is a quad 2-input multiplexer. It selects four bits of data from two sources under the control of a common Select input (S). The Enable input (E) is activeLOW. When E is HIGH, all of the outputs (Z) are forced LOW regardless of all other inputs. The VHC157 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input.
PAGE 3
74VHC157 Quad 2-Input Multiplexer Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1992 Fairchild Semiconductor Corporation 74VHC157 Rev. 1.2 www.fairchildsemi.
PAGE 4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.
PAGE 5
TA = –40°C to +85°C TA = 25°C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions Min. 1.50 3.0–5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage 3.0 LOW Level Output Voltage Min. IOH = –50µA 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 VIN = VIH or VIL IOL = 50µA 4.5 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 8mA 4.5 V 0.0 IOL = 4mA 3.0 V 0.3 x VCC 1.9 4.5 3.0 V 0.50 0.
PAGE 6
Symbol tPLH, tPHL Parameter Propagation Delay, In to Zn VCC (V) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay, S to Zn 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay, E to Zn 3.3 ± 0.3 5.0 ± 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance TA = –40°C to +85°C TA = 25°C Conditions Min. Typ. Max. Min. Max. Units CL = 15pF 6.2 9.7 1.0 11.5 ns CL = 50pF 8.7 13.2 1.0 15.0 CL = 15pF 4.1 6.4 1.0 7.5 CL = 50pF 5.6 8.4 1.0 9.5 CL = 15pF 8.4 13.2 1.0 15.
PAGE 7
4VHC157 Quad 2-Input Multiplexer Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1992 Fairchild Semiconductor Corporation 74VHC157 Rev. 1.2 www.fairchildsemi.
PAGE 8
74VHC157 Quad 2-Input Multiplexer Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D ©1992 Fairchild Semiconductor Corporation 74VHC157 Rev. 1.2 www.fairchildsemi.
PAGE 9
5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 ©1992 Fairchild Semiconductor Corporation 74VHC157 Rev. 1.2 www.fairchildsemi.com 9 74VHC157 Quad 2-Input Multiplexer Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.
PAGE 10
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