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74VHC161 4-Bit Binary Counter with Asynchronous Clear

May 2007

74VHC161 Rev. 1.4

74VHC161

4-Bit Binary Counter with Asynchronous Clear

Features

■

High Speed: f

MAX

185MHz (Typ.) at T

25°C

■

Synchronous counting and loading

■

High-speed synchronous expansion

■

Low power dissipation: I

4µA (Max.) at T

25°C

■

High noise immunity: V

NIH

NIL

28% V

(Min.)

■

Power down protection provided on all inputs

■

Low noise: V

OLP

0.8V (Max.)

■

Pin and function compatible with 74HC161

General Description

The VHC161 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The VHC161 is a high-speed

synchronous modulo-16 binary counter. This device is

synchronously presettable for application in program-

mable dividers and have two types of Count Enable

inputs plus a Terminal Count output for versatility in

forming synchronous multistage counters. The VHC161

has an asynchronous Master Reset input that overrides

all other inputs and forces the outputs LOW. An input

protection circuit insures that 0V to 7V can be applied to

the input pins without regard to the supply voltage. This

device can be used to interface 5V to 3V systems and

two supply systems such as battery backup. This circuit

prevents device destruction due to mismatched supply

and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number.

Connection Diagram Pin Description

Order Number

Package

Number Package Description

74VHC161M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names Description

CEP Count Enable Parallel Input

CET Count Enable Trickle Input

CP Clock Pulse Input

Asynchronous Master Reset Input

–P

Parallel Data Inputs

Parallel Enable Inputs

–Q

Flip-Flop Outputs

TC Terminal Count Output

Summary of content (11 pages)

PAGE 1
74VHC161 4-Bit Binary Counter with Asynchronous Clear tm Features General Description ■ High Speed: fMAX = 185MHz (Typ.) at TA = 25°C ■ Synchronous counting and loading The VHC161 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC161 is a high-speed synchronous modulo-16 binary counter.
PAGE 2
(CET)—determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.
PAGE 3
74VHC161 4-Bit Binary Counter with Asynchronous Clear Mode Select Table State Diagram Action on the Rising Clock Edge ( ) MR PE L X X X Reset (Clear) H L X X Load (Pn → Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) CET CEP H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
PAGE 4
Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current TSTG TL ±50mA Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation.
PAGE 5
TA = –40°C to +85°C TA = 25°C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions Min. 1.50 3.0–5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage 3.0 LOW Level Output Voltage Min. 0.50 IOH = –50µA 2.0 1.9 V 2.9 3.0 2.9 4.4 4.5 4.4 IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 VIN = VIH or VIL IOL = 50µA 4.5 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA 3.0 IOL = 8mA 4.5 V 0.3 x VCC 1.9 4.5 3.0 V 0.
PAGE 6
TA = –40° to +85°C TA = 25°C Symbol Parameter VCC (V) tPLH, tPHL Propagation Delay Time (CP–Qn) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CP–TC, Count) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CP–TC, Load) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CET–TC) 3.3 ± 0.3 5.0 ± 0.5 tPHL Propagation Delay Time (MR –Qn) 3.3 ± 0.3 5.0 ± 0.5 tPHL Propagation Delay Time (MR –TC) 3.3 ± 0.3 5.0 ± 0.5 fMAX Maximum Clock Frequency 3.3 ± 0.3 5.0 ± 0.
PAGE 7
TA = 25°C Symbol tS tS tS tH tH tH Parameter VCC (V)(4) Minimum Setup Time (Pn–CP) Minimum Setup Time (PE –CP) Minimum Setup Time (CEP or CET–CP) Minimum Hold Time (Pn–CP) Minimum Hold Time (PE –CP) Minimum Hold Time (CEP or CET–CP) tW(L), tW(H) Minimum Pulse Width CP (Count) tW(L) tREC Minimum Pulse Width (MR) Minimum Removal Time Typ. TA = –40°C to +85°C Guaranteed Minimum 3.3 5.5 6.5 5.0 4.5 4.5 3.3 8.0 9.5 5.0 5.0 6.0 3.3 7.5 9.0 5.0 5.0 6.0 3.3 1.0 1.0 5.0 1.0 1.0 3.
PAGE 8
74VHC161 4-Bit Binary Counter with Asynchronous Clear Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 3. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.
PAGE 9
74VHC161 4-Bit Binary Counter with Asynchronous Clear Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.
PAGE 10
5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 5. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 10 74VHC161 4-Bit Binary Counter with Asynchronous Clear Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.
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