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74VHC164 — 8-Bit Serial-In, Parallel-Out Shift Register

74VHC164 Rev. 1.4.0

February 2008

74VHC164

8-Bit Serial-In, Parallel-Out Shift Register

Features

■

High Speed: f

MAX

175MHz at V

■

Low power dissipation: I

4µA (max.) at T

25°C

■

High noise immunity: V

NIH

NIL

28% V

(min.)

■

Power down protection provided on all inputs

■

Low noise: V

OLP

0.8V (max.)

■

Pin and function compatible with 74HC164

General Description

The VHC164 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The VHC164 is a high-speed 8-Bit

Serial-In/Parallel-Out Shift Register. Serial data is

entered through a 2-input AND gate synchronous with

the LOW-to-HIGH transition of the clock. The device fea-

tures an asynchronous Master Reset which clears the

clock. An input protection circuit insures that 0V to 7V

can be applied to the input pins without regard to the

supply voltage. This device can be used to interface 5V

to 3V systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74VHC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC164SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Summary of content (10 pages)

PAGE 1
74VHC164 8-Bit Serial-In, Parallel-Out Shift Register Features General Description ■ High Speed: fMAX = 175MHz at VCC = 5V ■ Low power dissipation: ICC = 4µA (max.) at TA = 25°C The VHC164 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC164 is a high-speed 8-Bit Serial-In/Parallel-Out Shift Register.
PAGE 2
Logic Symbol Function Table Pin Description Pin Names Operating Mode Description A, B Data Inputs CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input (Active LOW) Q0–Q7 Outputs Inputs Outputs MR A B Q0 Q1–Q7 Reset (Clear) L X X L L–L Shift H L L L Q0–Q6 H L H L Q0–Q6 H H L L Q0–Q6 H H H H Q0–Q6 H = HIGH Voltage Levels L = LOW Voltage Levels Functional Description X = Immaterial The VHC164 is an edge-triggered 8-bit shift register with serial data
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.
PAGE 4
TA = –40°C to +85°C TA = 25°C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions Min. 1.50 3.0–5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage 3.0 LOW Level Output Voltage Min. IOH = –50µA 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 VIN = VIH or VIL IOL = 50µA 4.5 3.0 4.5 IOL = 8mA V 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA V 0.3 x VCC 1.9 4.5 2.0 V 0.50 0.
PAGE 5
TA = –40°C to +85°C TA = 25°C Symbol fMAX Parameter VCC (V) Maximum Clock Frequency 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CP–Qn) 3.3 ± 0.3 5.0 ± 0.5 tPHL Propagation Delay Time (MR–Qn) 3.3 ± 0.3 5.0 ± 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance Conditions Min. Typ. Max. Min. CL = 15pF, RL = 1kΩ 80 125 65 CL = 50pF, RL = 1kΩ 50 75 45 CL = 15pF, RL = 1kΩ 125 175 105 CL = 50pF, RL = 1kΩ 85 115 75 Max. MHz CL = 15pF, RL = 1kΩ 8.4 12.8 1.
PAGE 6
8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.
PAGE 7
4VHC164 — 8-Bit Serial-In, Parallel-Out Shift Register Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
74VHC164 — 8-Bit Serial-In, Parallel-Out Shift Register Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3.
PAGE 9
19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.
PAGE 10
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