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74VHC175 Quad D-Type Flip-Flop

May 2007

74VHC175 Rev. 1.2

74VHC175

Quad D-Type Flip-Flop

Features

■

High Speed: f

MAX

210MHz (Typ.) at V

■

Low power dissipation: I

4µA (Max.) at T

25°C

■

High noise immunity: V

NIH

NIL

28% V

(Min.)

■

Power down protection is provided on all inputs

■

Low noise: V

OLP

0.8V (Max.)

■

Pin and function compatible with 74HC175

General Description

The VHC175 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation.

The VHC175 is a high-speed quad D-type flip-flop. The

device is useful for general flip-flop requirements where

clock and clear inputs are common. The information on

the D inputs is stored during the LOW-to-HIGH clock

transition. Both true and complemented outputs of each

flip-flop are provided. A Master Reset input resets all flip-

flops, independent of the Clock or D inputs, when LOW.

An input protection circuit insures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number.

Connection Diagram Pin Description

Order Number

Package

Number Package Description

74VHC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names Description

–D

Data Inputs

CP Clock Pulse Input

MR Master Reset Input

–Q

Tr ue Outputs

–Q

Complement Outputs

Summary of content (9 pages)

PAGE 1
74VHC175 Quad D-Type Flip-Flop tm Features General Description ■ High Speed: fMAX = 210MHz (Typ.) at VCC = 5V ■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C The VHC175 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.
PAGE 2
Functional Description The VHC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-toHIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.
PAGE 4
TA = –40°C to +85°C TA = 25°C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions Min. 1.50 3.0–5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage Max. 3.0 IOH = –50µA LOW Level Output Voltage 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 IOH = –4mA 2.58 2.48 4.5 IOH = –8mA 3.94 3.80 3.0 VIN = VIH or VIL IOL = 50µA 4.5 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 8mA 4.5 V V 0.0 IOL = 4mA 3.0 V 0.3 x VCC 1.9 3.0 2.0 Units 0.50 0.
PAGE 5
TA = –40°C to +85°C TA = 25°C Symbol fMAX tPLH, tPHL tPLH, tPHL Parameter Maximum Clock Frequency Propagation Delay Time, (CP to Qn or Qn) Propagation Delay Time, (MR to Qn or Qn) tOSLH, tOSHL Output to Output Skew CIN Input Capacitance CPD Power Dissipation Capacitance VCC (V) Conditions Min. Typ. Max. Min. 3.3 ± 0.3 CL = 15pF 90 140 75 CL = 50pF 50 75 45 5.0 ± 0.5 CL = 15pF 150 210 125 CL = 50pF 85 115 75 Max. Units MHz MHz 3.3 ± 0.3 CL = 15pF 7.5 11.5 1.0 13.
PAGE 6
74VHC175 Quad D-Type Flip-Flop Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.
PAGE 7
4VHC175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.
PAGE 8
5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 8 74VHC175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.
PAGE 9
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