Datasheet

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74VHC273 Octal D-Type Flip-Flop

April 2007

74VHC273 Rev. 1.5

74VHC273

Octal D-Type Flip-Flop

Features

■

High Speed: f

MAX

165MHz (typ) at V

■

Low power dissipation: I

4µA (max) at T

25°C

■

High noise immunity: V

NIH

NIL

28% V

(min)

■

Power down protection is provided on all inputs

■

Low noise: V

OLP

0.9V (max)

■

Pin and function compatible with 74HC273

■

Leadless DQFN Package

General Description

The VHC273 is an advanced high speed CMOS Octal

D-type flip-flop fabricated with silicon gate CMOS tech-

nology. It achieves the high speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation.

The register has a common buffered Clock (CP) which is

fully edge-triggered. The state of each D input, one setup

time before the LOW-to-HIGH clock transition, is trans-

ferred to the corresponding flip-flop's Q output. The

Master Reset (MR

) input will clear all flip-flops simulta-

neously. All outputs will be forced LOW independently of

Clock or Data inputs by a LOW voltage level on the MR

input.

An input protection circuit insures that 0V to 7V can be

applied to the inputs pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Order Number

Package

Number Package Description

74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC273BQ

(Preliminary)

MLP020B

(Preliminary)

20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 4.5mm

74VHC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Summary of content (13 pages)

PAGE 1
74VHC273 Octal D-Type Flip-Flop tm Features General Description ■ High Speed: fMAX = 165MHz (typ) at VCC = 5V ■ Low power dissipation: ICC = 4µA (max) at TA = 25°C The VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
PAGE 2
74VHC273 Octal D-Type Flip-Flop Connection Diagrams Logic Symbols Pin Assignments for PDIP, SOIC, SOP, and TSSOP IEEE/IEC Pad Assignments for DQFN Function Table Operating Mode Inputs Outputs MR CP Dn Qn Reset (Clear) L X X L Load ‘1’ H H H Load ‘0’ H L L H = HIGH Voltage Level L = LOW Voltage Level (Top Through View) X = Immaterial = LOW-to-HIGH Transition Pin Descriptions Pin Names Description D0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs
PAGE 3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.
PAGE 4
Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC/GND Current ±75mA TSTG Storage Temperature –65°C to +150°C TL Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation.
PAGE 5
TA = 25°C Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VCC (V) Conditions Min. 2.0 1.50 3.0–5.5 0.7 x VCC 3.0 LOW Level Output Voltage Min. 0.50 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 V IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 VIN = VIH IOL = 50µA or VIL 4.5 3.0 4.5 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA IOL = 8mA V 0.3 x VCC 1.9 4.5 2.0 V 0.3 x VCC VIN = VIH IOH = –50µA or VIL Units 0.7 x VCC 3.0 3.
PAGE 6
TA = –40°C to +85°C TA = 25°C Symbol fMAX Parameter VCC (V) Maximum Clock Frequency 3.3 ± 0.3 Conditions 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CK – Q) 3.3 ± 0.3 5.0 ± 0.5 tPHL Propagation Delay Time (MR – Q) 3.3 ± 0.3 5.0 ± 0.5 tOSLH, tOSHL Output to Output Skew CIN Input Capacitance CPD Power Dissipation Capacitance 3.3 ± 0.3 (3) 5.0 ± 0.5 VCC (4) Min. Typ. Max. Min. CL = 15pF 75 120 65 CL = 50pF 50 75 45 CL = 15pF 120 165 100 CL = 50pF 80 110 70 Max.
PAGE 7
Tape Format for DQFN Package Designator Tape Section Number Cavities Cavity Status Cover Tape Status BQ Leader (Start End) 125 (typ.) Empty Sealed Carrier 2500/3000 Filled Sealed Trailer (Hub End) 75 (typ.) Empty Sealed Tape Dimensions Dimensions are in millimeters unless otherwise noted. Figure 2. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.
PAGE 8
74VHC273 Octal D-Type Flip-Flop Tape and Reel Specification (Continued) Reel Dimensions for DQFN Dimensions are in inches (millimeters) unless otherwise noted. Tape Size A B C D N W1 W2 12mm 13.0 (330) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 7.008 (178) 0.488 (12.4) 0.724 (18.4) Figure 3. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.
PAGE 9
74VHC273 Octal D-Type Flip-Flop Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.
PAGE 10
74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 5. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.
PAGE 11
74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 6. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B (Preliminary) ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.
PAGE 12
74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.
PAGE 13
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