Datasheet

74VHC27 — Triple 3-Input NOR Gate
©1994 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC27 Rev. 1.4.0
December 2007
74VHC27
Triple 3-Input NOR Gate
Features
High speed: t
PD
=
4.1ns (typ) at T
A
=
25°C
Low power dissipation: I
CC
=
2µA (max) at T
A
=
25°C
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min.)
Power down protection is provided on all inputs
Low noise: V
OLP
=
0.8V (max.)
Pin and function compatible with 74HC27
General Description
The VHC27 is an advanced high speed CMOS 3-Input
NOR Gate fabricated with silicon gate CMOS technol-
ogy. It achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 3 stages including
buffer output, which provide high noise immunity and
stable output. An input protection circuit insures that 0V
to 7V can be applied to the input pins without regard to
the supply voltage. This device can be used to interface
5V to 3V systems and two supply systems such as bat-
tery backup. This circuit prevents device destruction due
to mismatched supply and input voltages.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74VHC27M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
74VHC27SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC27MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide

Summary of content (9 pages)