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74VHC373 Octal D-Type Latch with 3-STATE Outputs

April 2007

74VHC373 Rev. 1.3

74VHC373

Octal D-Type Latch with 3-STATE Outputs

Features

■

High Speed: t

5.0ns (typ) @ V

■

High Noise Immunity: V

NIH

NIL

28% V

(Min.)

■

Power Down Protection is provided on all inputs

■

Low Noise: V

OLP

0.6V (Typ.)

■

Low Power Dissipation: I

4µA (Max) @ T

25°C

■

Pin and Function Compatible with 74HC373

General Description

The VHC373 is an advanced high speed CMOS octal

D-type latch with 3-STATE output fabricated with silicon

gate CMOS technology. It achieves the high speed oper-

ation similar to equivalent Bipolar Schottky TTL while

maintaining the CMOS low power dissipation. This 8-bit

D-type latch is controlled by a latch enable input (LE)

and an output enable input (OE

). The latches appear

transparent to data when latch enable (LE) is HIGH.

When LE is LOW, the data that meets the setup time is

LATCHED. When the OE

input is HIGH, the eight

outputs are in a high impedance state.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery back

up. This circuit prevents device destruction due to mis-

matched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram Pin Descriptions

Order Number

Package

Number Package Description

74VHC373M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names Description

–D

Data Inputs

LE Latch Enable Input

Output Enable Input

–O

3-STATE Outputs

Summary of content (9 pages)

PAGE 1
74VHC373 Octal D-Type Latch with 3-STATE Outputs tm Features General Description ■ High Speed: tPD = 5.0ns (typ) @ VCC = 5V ■ High Noise Immunity: VNIH = VNIL = 28% VCC (Min.) The VHC373 is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
PAGE 2
Functional Description IEEE/IEC The VHC373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE.
PAGE 3
Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC/GND Current ±75mA TSTG Storage Temperature –65°C to +150°C TL Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation.
PAGE 4
TA = 25°C Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VCC (V) Conditions Min. 2.0 1.50 3.0–5.5 0.7 x VCC 3.0 LOW Level Output Voltage Min. 0.50 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 V IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 VIN = VIH IOL = 50µA or VIL 4.5 3.0 4.5 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA IOL = 8mA V 0.3 x VCC 1.9 4.5 2.0 V 0.3 x VCC VIN = VIH IOH = –50µA or VIL Units 0.7 x VCC 3.0 3.
PAGE 5
TA = –40°C to +85°C TA = +25°C Symbol Parameter tPLH, tPHL Propagation Delay Time (LE to On) VCC (V) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (D to On) 3.3 ± 0.3 5.0 ± 0.5 tPZL, tPZH 3-STATE Output Enable Time 3.3 ± 0.3 RL = 1kΩ tOSLH, tOSHL Output to Output Skew 3.3 ± 0.3 Max. Min. Max. Units ns CL = 15pF 7.0 11.0 1.0 13.0 CL = 50pF 9.5 14.5 1.0 16.5 CL = 15pF 4.9 7.2 1.0 8.5 CL = 50pF 6.4 9.2 1.0 10.5 CL = 15pF 7.3 11.4 1.0 13.5 CL = 50pF 9.8 14.
PAGE 6
74VHC373 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 2. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1993 Fairchild Semiconductor Corporation 74VHC373 Rev. 1.3 www.fairchildsemi.
PAGE 7
4VHC373 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1993 Fairchild Semiconductor Corporation 74VHC373 Rev. 1.3 www.fairchildsemi.
PAGE 8
74VHC373 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1993 Fairchild Semiconductor Corporation 74VHC373 Rev. 1.3 www.fairchildsemi.
PAGE 9
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