Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Counter Binary counter 74VHC Negative slope 210 MHz TSSOP 16

74VHC4040 12-Stage Binary Counter

May 2007

74VHC4040 Rev. 1.3

74VHC4040

12-Stage Binary Counter

Features

■

High speed; f

MAX

210MHz at V

■

Low power dissipation: I

4µA (Max.) at T

25°C

■

High noise immunity: V

NIH

NIL

28% V

(Min.)

■

Power down protection is provided on all inputs

■

Wide operating voltage range: V

(Opr.)

2V – 5.5V

■

Low noise: V

OLP

0.8V (Max.)

■

Pin and function compatible with 74HC4040

General Description

The VHC4040 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The VHC4040 is a 12-stage counter

which increments on the negative edge of the input clock

and all outputs are reset to a low level by applying a

logical high on the reset input. An input protection circuit

insures that 0V to 7V can be applied to the inputs without

regard to the supply voltage. This device can be used to

interface 5V to 3V systems and two supply systems such

as battery backup. This circuit prevents device destruc-

tion due to mismatched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number.

Connection Diagram Pin Descriptions

Order Number

Package

Number Package Description

74VHC4040M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC4040MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Pin Names Description

–Q

Flip-Flop Outputs

Negative Edged Triggered Clock

MR Master Reset

Summary of content (9 pages)

PAGE 1
74VHC4040 12-Stage Binary Counter tm Features General Description ■ High speed; fMAX = 210MHz at VCC = 5V ■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C The VHC4040 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
PAGE 2
74VHC4040 12-Stage Binary Counter Logic Symbols IEEE/IEC Logic Diagram ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.
PAGE 3
74VHC4040 12-Stage Binary Counter Timing Diagram ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.
PAGE 4
Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current TSTG TL ±75mA Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation.
PAGE 5
TA = –40°C to +85°C TA = 25°C Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VCC (V) Conditions Min. 2.0 1.50 3.0 – 5.5 0.7 x VCC 3.0 LOW Level Output Voltage IOH = –50µA Quiescent Supply Current ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 2.9 3.0 2.9 4.4 4.5 4.4 2.58 2.48 3.94 3.80 4.5 ICC 1.9 IOH = –8mA 3.0 Input Leakage Current 2.0 IOH = –4mA VIN = VIH or VIL IOL = 50µA IOL = 8mA V 0.0 0.
PAGE 6
TA = –40°C to +85°C TA = +25°C Symbol Parameter VCC (V) Conditions tPLH, tPHL Propagation Delay Time to Q1 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL tPHL Propagation Delay Time between Stages from Qn to Qn+1 Propagation Delay Time MR–Qn 3.3 ± 0.3 Maximum Clock Frequency 5.0 ± 0.5 3.3 ± 0.3 3.3 ± 0.3 5.0 ± 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance Typ. Max. Min. CL = 15pF 7.5 11.9 1.0 14.0 CL = 50pF 10.0 15.4 1.0 17.5 CL = 15pF 4.8 7.3 1.0 8.5 CL = 50pF 6.3 9.
PAGE 7
4VHC4040 12-Stage Binary Counter Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.
PAGE 8
5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 2. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 8 74VHC4040 12-Stage Binary Counter Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.
PAGE 9
® ACEx Across the board. Around the world.