Datasheet

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March 1993

Revised May 2005

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs

74VHC574

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description

The VHC574 is an advanced high speed CMOS octal flip-

flop with 3-STATE output fabricated with silicon gate CMOS

technology. It achieves the high speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. This 8-bit D-type flip-flop is

controlled by a clock input (CP) and an output enable input

(OE

). When the OE input is HIGH, the eight outputs are in

a high impedance state.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supply systems such as battery back up. This cir-

cuit prevents device destruction due to mismatched supply

and input voltages.

Features

■ High Speed: t

5.6 ns (typ) at V

■ High Noise Immunity: V

NIH

NIL

28% V

(Min)

■ Power Down Protection is provided on all inputs

■ Low Noise: V

OLP

0.6V (typ)

■ Low Power Dissipation: I

4 A (Max) @ T

25 C

■ Pin and Function Compatible with 74HC574

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

74VHC574M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC574SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Names Description

–D

Data Inputs

CP Clock Pulse Input

3-STATE Output Enable Input

–O

3-STATE Outputs

Summary of content (8 pages)

PAGE 1
Revised May 2005 74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description The VHC574 is an advanced high speed CMOS octal flipflop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE).
PAGE 2
74VHC574 Functional Description Truth Table The VHC574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs.
PAGE 3
Recommended Operating Conditions (Note 2) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r 0.
PAGE 4
74VHC574 AC Electrical Characteristics Symbol VCC (V) Parameter tPLH Propagation Delay tPHL Time (CP to On) 3.3 r 0.3 5.0 r 0.5 tPZL 3-STATE Output tPZH Enable Time 25qC TA Min 3.3 r 0.3 5.0 r 0.5 TA 40qC to 85qC Typ Max Min Max 8.5 13.2 1.0 15.5 11.0 16.7 1.0 19.0 5.6 8.6 1.0 10.0 7.1 10.6 1.0 12.0 8.2 12.8 1.0 15.0 10.7 16.3 1.0 18.5 5.9 9.0 1.0 10.5 7.4 11.0 1.0 12.5 tPLZ 3-STATE Output 3.3 r 0.3 11.0 15.0 1.0 17.0 tPHZ Disable Time 5.
PAGE 5
74VHC574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.
PAGE 6
74VHC574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.
PAGE 7
4VHC574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.
PAGE 8
74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.