Datasheet

74VHC595 8-Bit Shift Register with Output Latches
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC595 Rev. 1.2 2
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Truth Table
Pin Names Description
SER Serial Data Input
SCK Shift Register Clock Input
(Active rising edge)
RCK Storage Register Clock Input
(Active rising edge)
SCLR
Reset Input
G
3-STATE Output Enable Input
(Active LOW)
Q
A
– Q
H
Parallel Data Outputs
Q’
H
Serial Data Output
Inputs
FunctionSER RCK SCK SCLR
G
XXXXHQ
A
thru Q
H
3-STATE
XXXXLQ
A
thru Q
H
outputs enabled
XXXLLShift Register cleared: Q ′
H
= 0
LX ↑ HLShift Register clocked: Q
N
= Q
n-1
, Q
0
= SER = L
HX ↑ HLShift Register clocked: Q
N
= Q
n-1
, Q
0
= SER = H
X ↑ XHLContents of Shift Register transferred to output latches