Datasheet

74VHC595 8-Bit Shift Register with Output Latches
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC595 Rev. 1.2 7
AC Electrical Characteristics
Notes:
3. Parameter guaranteed by design. t
OSLH
= | t
PLH
max – t
PLH
min|; t
OSHL
= | t
PHL
max – t
PHL
min|
4. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
I
CC
(Opr.) = C
PD
• V
CC
• f
IN
+ I
CC
Symbol Parameter V
CC
(V) Conditions
T
A
= +25°C
T
A
= –40°C
to +85°C
UnitsMin. Typ. Max. Min. Max.
t
PLH
, t
PHL
Propagation Delay Time,
RCK to Q
A
–Q
H
3.3 ± 0.3 C
L
= 15pF 7.7 11.9 1.0 13.5 ns
C
L
= 50pF 10.2 15.4 1.0 17.0
5.0 ± 0.5 C
L
= 15pF 5.4 7.4 1.0 8.5 ns
C
L
= 50pF 6.9 9.4 1.0 10.5
t
PLH
, t
PHL
Propagation Delay Time,
SCK–Q'H
3.3 ± 0.3 C
L
= 15pF 8.8 13.0 1.0 15.0 ns
C
L
= 50pF 11.3 16.5 1.0 18.5
5.0 ± 0.5 C
L
= 15pF 6.2 8.2 1.0 9.4 ns
C
L
= 50pF 7.7 10.2 1.0 11.4
t
PHL
Propagation Delay Time,
SCLR –Q'H
3.3 ± 0.3 C
L
= 15pF 8.4 12.8 1.0 13.7 ns
C
L
= 50pF 10.9 16.3 1.0 17.2
5.0 ± 0.5 C
L
= 15pF 5.9 8.0 1.0 9.1 ns
C
L
= 50pF 7.4 10.0 1.0 11.1
t
PZL
, t
PZH
Output Enable Time,
G to Q
A
–Q
H
3.3 ± 0.3 R
L
= 1kΩ C
L
= 15pF 7.5 11.5 1.0 13.5 ns
C
L
= 50pF 9.0 15.0 1.0 17.0
5.0 ± 0.5 C
L
= 15pF 4.8 8.6 1.0 10.0 ns
C
L
= 50pF 8.3 10.6 1.0 12.0
t
PLZ
, t
PHZ
Output Disable Time,
G to Q
A
–Q
H
3.3 ± 0.3 R
L
= 1kΩ C
L
= 50pF 12.1 15.7 1.0 16.2 ns
5.0 ± 0.5 C
L
= 50pF 7.6 10.3 1.0 11.0
f
MAX
Maximum Clock
Frequency
3.3 ± 0.3 C
L
= 15pF 80 150 70 MHz
C
L
= 50pF 55 130 50
5.0 ± 0.5 C
L
= 15pF 135 185 115 MHz
C
L
= 50pF 95 155 85
t
OSLH
, t
OSHL
Output to Output Skew 3.3 ± 0.3
(3)
C
L
= 50pF 1.5 1.5 ns
5.0 ± 0.5 C
L
= 50pF 1.0 1.0
C
IN
Input Capacitance V
CC
= Open 5.0 10 10 pF
C
OUT
Output Capacitance V
CC
= 5.0V 6.0 pF
C
PD
Power Dissipation
Capacitance
(4)
87 pF