Datasheet

74VHC595 8-Bit Shift Register with Output Latches
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC595 Rev. 1.2 8
AC Operating Requirements
Symbol Parameter V
CC
(V)
T
A
= 25°C
T
A
= –40°C
to +85°C
UnitsTyp. Guaranteed Minimum
t
S
Minimum Setup Time (SER–SCK) 3.3 ± 0.3 3.5 3.5 ns
5.0 ± 0.5 3.0 3.0
t
S
Minimum Setup Time (SCK–RCK) 3.3 ± 0.3 8.0 8.5 ns
5.0 ± 0.5 5.0 5.0
t
S
Minimum Setup Time (SCLR–RCK) 3.3 ± 0.3 8.0 9.0 ns
5.0 ± 0.5 5.0 5.0
t
H
Minimum Hold Time (SER–SCK) 3.3 ± 0.3 1.5 1.5 ns
5.0 ± 0.5 2.0 2.0
t
H
Minimum Hold Time (SCK–RCK) 3.3 ± 0.3 0.0 0.0 ns
5.0 ± 0.5 0.0 0.0
t
H
Minimum Hold Time (SCLR–RCK) 3.3 ± 0.3 0.0 0.0 ns
5.0 ± 0.5 0.0 0.0
t
W(L)
Minimum Pulse Width (SCLR) 3.3 ± 0.3 5.0 5.0 ns
5.0 ± 0.5 5.0 5.0
t
W(L)
, t
W(H)
Minimum Pulse Width (SCK) 3.3 ± 0.3 5.0 5.0 ns
5.0 ± 0.5 5.0 5.0
t
W(L)
, t
W
(H) Minimum Pulse Width (RCK) 3.3 ± 0.3 5.0 5.0 ns
5.0 ± 0.5 5.0 5.0
t
rem
Minimum Removal Time (SCLR–SCK) 3.3 ± 0.3 3.0 3.0 ns
5.0 ± 0.5 2.5 2.5