Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFCA35N60, MOSFET

November 2013

FCA35N60 — N-Channel SuperFET

MOSFET

FCA35N60 Rev. C1

www.fairchildsemi.com

FCA35N60

N-Channel SuperFET

MOSFET

600 V, 35 A, 98 mΩ

Features

• 650V @ T

= 150°C

•Typ. R

DS(on)

= 79 mΩ

• Ultra Low Gate Charge (Typ. Q

= 139 nC )

• Low Effective Output Capacitance (Typ. C

oss(eff.)

= 340 pF )

• 100% Avalanche Tested

Applications

• Solar Inverter

• AC-DC Power Supply

Description

SuperFET

MOSFET is Fairchild Semiconductor’s first genera-

tion of high voltage super-junction (SJ) MOSFET family that is

utilizing charge balance technology for outstanding low on-

resistance and lower gate charge performance. This technology

is tailored to minimize conduction loss, provide superior switch-

ing performance, dv/dt rate and higher avalanche energy. Con-

sequently, SuperFET MOSFET is very suitable for the switching

power applications such as PFC, server/telecom power, FPD

TV power, ATX power and industrial power applications.

TO-3PN

MOSFET Maximum Ratings T

= 25

C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FCA35N60 Unit

DSS

Drain to Source Voltage 600 V

GSS

Gate-Soure voltage ±30 V

D r a i n C u r r e n t

- Continuous (T

= 25

C) 35

- Continuous (T

= 100

C) 22.2

D r a i n C u r r e n t - P u l s e d (Note 1) 105 A

Single Pulsed Avalanche Energy (Note 2) 1455 mJ

Avalanche Current (Note 1) 35 A

Repetitive Avalanche Energy (Note 1) 31.25 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 20 V/ns

Power Dissipation

= 25

C) 312.5 W

- Derate Above 25

C2.5W/

, T

STG

Operating and Storage Temperature Range -55 to +150

Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds

300

Symbol Parameter FCA35N60 Unit

θJC

Thermal Resistance, Junction to Case, Max. 0.4

C/W

θJA

Thermal Resistance, Junction to Ambient, Max. 42

Summary of content (8 pages)

PAGE 1
FCA35N60 N-Channel SuperFET® MOSFET 600 V, 35 A, 98 mΩ Features Description • 650V @ TJ = 150°C SuperFET® MOSFET is Fairchild Semiconductor’s first generation of high voltage super-junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low onresistance and lower gate charge performance. This technology is tailored to minimize conduction loss, provide superior switching performance, dv/dt rate and higher avalanche energy.
PAGE 2
Part Number FCA35N60 Top Mark FCA35N60 Electrical Characteristics Symbol Package TO-3PN Packing Method Tube Reel Size N/A Tape Width N/A Quantity 30 units TC = 25oC unless otherwise noted. Parameter Test Conditions Min. Typ. Max.
PAGE 3
Figure 1. On-Region Characteristics 200 200 VGS = 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V 100 ID, Drain Current[A] 100 ID, Drain Current[A] Figure 2. Transfer Characteristics 10 1 o 150 C 10 o -55 C o 25 C *Notes: 1. 250μs Pulse Test *Notes: 1. VDS = 20V 2. 250μs Pulse Test o 0.3 0.1 2. TC = 25 C 1 VDS, Drain-Source Voltage[V] 10 1 20 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 5 6 7 8 VGS, Gate-Source Voltage[V] 500 IS, Reverse Drain Current [A] 0.
PAGE 4
Figure 8. On-Resistance Variation vs. Temperature 1.15 3.0 1.10 2.5 RDS(on), [Normalized] Drain-Source On-Resistance BVDSS, [Normalized] Drain-Source Breakdown Voltage Figure 7. Breakdown Voltage Variation vs. Temperature 1.05 1.00 0.95 *Notes: 1. VGS = 0V 2. ID = 250μA 0.90 0.85 -100 -50 0 50 100 150 o TJ, Junction Temperature [ C] 2.0 1.5 1.0 0.0 -100 200 Figure 9. Maximum Safe Operating Area *Notes: 1. VGS = 10V 2. ID = 17.5A 0.
PAGE 5
FCA35N60 — N-Channel SuperFET® MOSFET IG = const. Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS VDD VGS VGS DUT V 10V GS 90% 10% td(on) tr t on td(off) tf t off Figure 13. Resistive Switching Test Circuit & Waveforms VGS Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms ©2009 Fairchild Semiconductor Corporation FCA35N60 Rev. C1 5 www.fairchildsemi.
PAGE 6
FCA35N60 — N-Channel SuperFET® MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15.
PAGE 7
FCA35N60 — N-Channel SuperFET® MOSFET Mechanical Dimensions Figure 16. TO3, 3-Lead, Plastic, EIAJ SC-65 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.