Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFCH47N60_F133, MOSFET

December 2013

FCH47N60 Rev. C2

www.fairchildsemi.com

FCH47N60 — N-Channel SuperFET

MOSFET

FCH47N60

N-Channel SuperFET

MOSFET

600 V, 47 A, 70 mΩ

Features

•650 V @ T

= 150°C

•Typ. R

DS(on)

= 58 mΩ

• Ultra Low Gate Charge (Typ. Q

= 210 nC)

• Low Effective Output Capacitance (Typ. C

oss(eff.)

= 420 pF)

• 100% Avalanche Tested

•RoHS Compliant

Applications

• Solar Inverter

• AC-DC Power Supply

Description

SuperFET

MOSFET is Fairchild Semiconductor’s first genera-

tion of high voltage super-junction (SJ) MOSFET family that is

utilizing charge balance technology for outstanding low on-

resistance and lower gate charge performance. This technology

is tailored to minimize conduction loss, provide superior switch-

ing performance, dv/dt rate and higher avalanche energy. Con-

sequently, SuperFET MOSFET is very suitable for the switching

power applications such as PFC, server/telecom power, FPD

TV power, ATX power and industrial power applications.

TO-247

MOSFET Maximum Ratings T

= 25°C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FCH47N60_F133 Unit

DSS

Drain to Source Voltage 600 V

Drain Current

Continuous (T

= 25°C) 47

Continuous (T

= 100°C) 29.7

Drain Current Pulsed (Note 1) 141 A

GSS

Gate to Source Voltage ±30 V

Single Pulsed Avalanche Energy (Note 2) 1800 mJ

Avalanche Current (Note 1) 47 A

Repetitive Avalanche Energy (Note 1) 41.7 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3) 4.5 V/ns

Power Dissipation

= 25°C) 417 W

Derate Above 25°C 3.33 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum Lead Temperature for Soldering,

1/8” from Case for 5 Seconds

300 °C

Symbol Parameter FCH47N60_F133 Unit

θJC

Thermal Resistance, Junction to Case, Max. 0.3 °C/W

θJA

Thermal Resistance, Case-to-Sink, Typ. 0.24 °C/W

θJA

Thermal Resistance, Junction to Ambient, Max. 41.7 °C/W

Summary of content (8 pages)

PAGE 1
FCH47N60 N-Channel SuperFET® MOSFET 600 V, 47 A, 70 mΩ Features Description • 650 V @ TJ = 150°C SuperFET® MOSFET is Fairchild Semiconductor’s first generation of high voltage super-junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low onresistance and lower gate charge performance. This technology is tailored to minimize conduction loss, provide superior switching performance, dv/dt rate and higher avalanche energy.
PAGE 2
Part Number FCH47N60_F133 Top Mark FCH47N60 Package TO-247 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 30 units Electrical Characteristics TC = 25°C unless otherwise noted. Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS = 0 V, ID = 250 μA, TC = 25°C 600 - - V VGS = 0 V, ID = 250 μA, TC = 150°C - 650 - V ID = 250 μA, Referenced to 25°C - 0.
PAGE 3
VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V Top : ID, Drain Current [A] 10 2 ID , Drain Current [A] 2 1 10 ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ 0 10 -1 0 10 10 150℃ 1 10 -55℃ ※ Note 1. VDS = 40V 2. 250μ s Pulse Test 0 10 2 1 10 25℃ 10 4 8 10 Figure 2. Transfer Characteristics 0.20 IDR , Reverse Drain Current [A] RDS(ON) [Ω ],Drain-Source On-Resistance Figure 1. On-Region Characteristics 0.15 VGS = 10V 0.10 VGS = 20V 0.
PAGE 4
3.0 RDS(ON), (Normalized) Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 150 2.5 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 47 A 0.5 0.0 -100 200 -50 0 o 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FCH47N60 — N-Channel SuperFET® MOSFET IG = const. Figure 13. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on tf t off Figure 14. Resistive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp tp Time Figure 15.
PAGE 6
FCH47N60 — N-Channel SuperFET® MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 16.
PAGE 7
FCH47N60 — N-Channel SuperFET® MOSFET Mechanical Dimensions Figure 17. TO-247, Molded, 3-Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.