Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFCP25N60N_F102, MOSFET

November 2013

FCP25N60N — N-Channel SupreMOS

MOSFET

FCP25N60N Rev. C1

www.fairchildsemi.com

FCP25N60N

N-Channel SupreMOS

MOSFET

600 V, 25 A, 125 mΩ

Features

•R

DS(on)

= 107 mΩ (Typ.) @ V

= 10 V, I

= 12.5 A

• Ultra Low Gate Charge (Typ. Q

= 57 nC)

• Low Effective Output Capacitance (Typ. C

oss(eff.)

= 262 pF)

• 100% Avalanche Tested

• RoHS Compliant

Application

• Solar Inverter

• AC-DC Power Supply

Description

The SupreMOS

MOSFET is Fairchild Semiconductor’s next

generation of high voltage super-junction (SJ) technology

employing a deep trench filling process that differentiates it from

the conventional SJ MOSFETs. This advanced technology and

precise process control provides lowest Rsp on-resistance,

superior switching performance and ruggedness. SupreMOS

MOSFET is suitable for high frequency switching power con-

verter applications such as PFC, server/telecom power, FPD TV

power, ATX power, and industrial power applications.

Absolute Maximum Ratings T

= 25

C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FCP25N60N_F102 Unit

DSS

Drain to Source Voltage 600 V

GSS

Gate to Source Voltage ±30 V

Drain Current

- Continuous (T

= 25

C) 25

- Continuous (T

= 100

C) 16

Drain Current - Pulsed (Note 1) 75 A

Single Pulsed Avalanche Energy (Note 2) 861 mJ

Avalanche Current (Note 1) 8.3 A

Repetitive Avalanche Energy (Note 1) 2.2 mJ

dv/dt

Peak Diode Recovery dv/dt (Note 3) 20

V/ns

MOSFET dv/dt 100

Power Dissipation

= 25

C) 216 W

- Derate Above 25

C1.72W/

, T

STG

Operating and Storage Temperature Range -55 to +150

Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds

300

Symbol Parameter FCP25N60N_F102 Unit

θJC

Thermal Resistance, Junction to Case, Max. 0.58

C/W

θJA

Thermal Resistance, Junction to Ambient, Max. 62.5

TO-220

Summary of content (8 pages)

PAGE 1
FCP25N60N N-Channel SupreMOS® MOSFET 600 V, 25 A, 125 mΩ Features Description • RDS(on) = 107 mΩ (Typ.) @ VGS = 10 V, ID = 12.5 A The SupreMOS® MOSFET is Fairchild Semiconductor’s next generation of high voltage super-junction (SJ) technology employing a deep trench filling process that differentiates it from the conventional SJ MOSFETs. This advanced technology and precise process control provides lowest Rsp on-resistance, superior switching performance and ruggedness.
PAGE 2
Part Number FCP25N60N_F102 Top Mark FCP25N60N Package TO-220 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 50 units Electrical Characteristics TC = 25oC unless otherwise noted. Symbol Parameter Test Conditions Min. Typ. Max. Unit 600 - - V - 0.
PAGE 3
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 100 100 10V 8V 6V 4V ID, Drain Current[A] ID, Drain Current[A] VGS = 15V 10 o 25 C 10 o 150 C o -55 C *Notes: 1. 250μs Pulse Test 1 *Notes: 1. VDS = 20V 2. 250μs Pulse Test o 2. TC = 25 C 0.3 0.05 0.1 1 10 VDS, Drain-Source Voltage[V] 1 30 2 4 6 VGS, Gate-Source Voltage[V] Figure 4. Body Diode Forward Voltage Variation vs.
PAGE 4
Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 3.0 RDS(on), [Normalized] Drain-Source On-Resistance BVDSS, [Normalized] Drain-Source Breakdown Voltage 1.2 1.1 1.0 0.9 *Notes: 1. VGS = 0V 2. ID = 1mA 0.8 -100 -50 0 50 100 150 o TJ, Junction Temperature [ C] 2.0 1.5 1.0 *Notes: 1. VGS = 10V 2. ID = 12.5A 0.5 0.0 -100 200 -50 0 50 100 150 o TJ, Junction Temperature [ C] Figure 9. Maximum Safe Operating Area Figure 10.
PAGE 5
FCP25N60N — N-Channel SupreMOS® MOSFET IG = const. Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS VDD VGS VGS DUT V 10V GS 90% 10% td(on) tr t on td(off) tf t off Figure 13. Resistive Switching Test Circuit & Waveforms VGS Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms ©2010 Fairchild Semiconductor Corporation FCP25N60N Rev. C1 5 www.fairchildsemi.
PAGE 6
FCP25N60N — N-Channel SupreMOS® MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15.
PAGE 7
FCP25N60N — N-Channel SupreMOS® MOSFET Mechanical Dimensions Figure 16. TO-220, Molded, 3-Lead, Jedec Variation AB (Delta) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.