Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFCPF380N60E, MOSFET

November 2013

FCP9N60N / FCPF9N60NT — N-Channel SupreMOS

MOSFET

FCP9N60N / FCPF9N60NT Rev. C1

www.fairchildsemi.com

TO-220

TO-220F

FCP9N60N / FCPF9N60NT

N-Channel SupreMOS

MOSFET

600 V, 9 A, 385 mΩ

Features

•R

DS(on)

= 330 mΩ (Typ.) @ V

= 10 V, I

= 4.5 A

• Ultra Low Gate Charge (Typ. Q

= 22 nC)

• Low Effective Output Capacitance (Typ. C

oss(eff.)

= 106 pF)

• 100% Avalanche Tested

• RoHS Compliant

Application

• LCD/LED/PDP TV

• Lighting

• Solar Inverter

• AC-DC Power Supply

Description

The SupreMOS

MOSFET is Fairchild Semiconductor’s next

generation of high voltage super-junction (SJ) technology

employing a deep trench filling process that differentiates it from

the conventional SJ MOSFETs. This advanced technology and

precise process control provides lowest Rsp on-resistance,

superior switching performance and ruggedness. SupreMOS

MOSFET is suitable for high frequency switching power con-

verter applications such as PFC, server/telecom power, FPD TV

power, ATX power, and industrial power applications.

Absolute Maximum Ratings T

= 25

C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FCP9N60N FCPF9N60NT Unit

DSS

Drain to Source Voltage 600 V

GSS

Gate to Source Voltage ±30 V

Drain Current

- Continuous (T

= 25

C) 9.0 9.0*

- Continuous (T

= 100

C) 5.7 5.7*

Drain Current - Pulsed (Note 1) 27 27* A

Single Pulsed Avalanche Energy (Note 2) 135 mJ

Avalanche Current (Note 1) 3 A

Repetitive Avalanche Energy (Note 1) 0.83 mJ

dv/dt

MOSFET dv/dt 100 V/ns

Peak Diode Recovery dv/dt (Note 3) 20 V/ns

Power Dissipation

= 25

C) 83.3 29.8 W

- Derate Above 25

C 0.67 0.24 W/

, T

STG

Operating and Storage Temperature Range -55 to +150

Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds

300

Symbol Parameter FCP9N60N FCPF9N60NT Unit

θJC

Thermal Resistance, Junction to Case, Max. 1.5 4.2

C/W

θJA

Thermal Resistance, Junction to Ambient, Max. 62.5 62.5

*Drain current limited by maximum junction temperature.

Summary of content (10 pages)

PAGE 1
FCP9N60N / FCPF9N60NT N-Channel SupreMOS® MOSFET 600 V, 9 A, 385 mΩ Features Description • RDS(on) = 330 mΩ (Typ.) @ VGS = 10 V, ID = 4.5 A The SupreMOS® MOSFET is Fairchild Semiconductor’s next generation of high voltage super-junction (SJ) technology employing a deep trench filling process that differentiates it from the conventional SJ MOSFETs. This advanced technology and precise process control provides lowest Rsp on-resistance, superior switching performance and ruggedness.
PAGE 2
Part Number FCP9N60N Top Mark FCP9N60N Package TO-220 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 50 units FCPF9N60NT FCPF9N60NT TO-220F Tube N/A N/A 50 units Electrical Characteristics TC = 25oC unless otherwise noted. Symbol Parameter Test Conditions Min. Typ. Max. Unit 600 - - V - 0.
PAGE 3
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 60 VGS = 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V 5.0 V 10 ID, Drain Current[A] ID, Drain Current[A] 100 1 10 o o 150 C 25 C o -55 C 1 *Notes: 1. 250μs Pulse Test *Notes: 1. VDS = 20V 2. 250μs Pulse Test o 0.1 0.1 2. TC = 25 C 1 VDS, Drain-Source Voltage[V] 10 0.1 20 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 4 6 VGS, Gate-Source Voltage[V] 100 IS, Reverse Drain Current [A] 1.0 0.
PAGE 4
Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 3.0 RDS(on), [Normalized] Drain-Source On-Resistance BVDSS, [Normalized] Drain-Source Breakdown Voltage 1.2 1.1 1.0 0.9 *Notes: 1. VGS = 0V 2. ID = 1mA 0.8 -100 -50 0 50 100 150 o TJ, Junction Temperature [ C] 2.5 2.0 1.5 1.0 0.0 -100 200 Figure 9. Maximum Safe Operating Area for FCPF9N60N *Notes: 1. VGS = 10V 2. ID = 4.5A 0.5 -50 0 50 100 150 o TJ, Junction Temperature [ C] Figure 10.
PAGE 5
FCP9N60N / FCPF9N60NT — N-Channel SupreMOS® MOSFET Typical Performance Characteristics (Continued) Figure 12. Transient Thermal Response Curve for FCP9N60N o ZθJC (t), Thermal Response Thermal Response [ZθJC[ ]C/W] 2 1 0.5 0.2 0.1 0.1 PDM 0.05 t1 0.02 0.01 t2 *Notes: Single pulse o 1. ZθJC(t) = 1.5 C/W Max. 2. Duty Factor, D= t1/t2 3. TJM - TC = PDM * ZθJC(t) 0.01 0.005 -5 10 -4 10 -3 -2 10 10 Rectangular Pulse Duration t1, Rectangular Pulse Duration[sec] [sec] -1 10 1 Figure 13.
PAGE 6
FCP9N60N / FCPF9N60NT — N-Channel SupreMOS® MOSFET IG = const. Figure 14. Gate Charge Test Circuit & Waveform VDS RG RL VDS VDD VGS VGS DUT V 10V GS 90% 10% td(on) tr t on td(off) tf t off Figure 15. Resistive Switching Test Circuit & Waveforms VGS Figure 16. Unclamped Inductive Switching Test Circuit & Waveforms ©2009 Fairchild Semiconductor Corporation FCP9N60N / FCPF9N60NT Rev. C1 6 www.fairchildsemi.
PAGE 7
FCP9N60N / FCPF9N60NT — N-Channel SupreMOS® MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 17.
PAGE 8
FCP9N60N / FCPF9N60NT — N-Channel SupreMOS® MOSFET Mechanical Dimensions Figure 18. TO-220, Molded, 3-Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 9
FCP9N60N / FCPF9N60NT — N-Channel SupreMOS® MOSFET Mechanical Dimensions Figure 19. TO220, Molded, 3-Lead, Full Pack, EIAJ SC91, Straight Lead Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 10
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.