Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDA18N50, MOSFET

November 2013

FDA18N50 — N-Channel UniFET

MOSFET

FDA18N50 Rev. C1

www.fairchildsemi.com

FDA18N50

N-Channel UniFET

MOSFET

500 V, 19 A, 265 m

Features

•R

DS(on)

= 265 m (Max.) @ V

= 10 V, I

= 9.5 A

• Low Gate Charge (Typ. 45 nC)

•Low C

rss

(Typ. 25 pF)

• 100% Avalanche Tested

Applications

•PDP TV

• Uninterruptible Power Supply

• AC-DC Power Supply

Description

UniFET

MOSFET is Fairchild Semiconductor’s high voltage

MOSFET family based on planar stripe and DMOS technology.

This MOSFET is tailored to reduce on-state resistance, and to

provide better switching performance and higher avalanche

energy strength. This device family is suitable for switching

power converter applications such as power factor correction

(PFC), flat panel display (FPD) TV power, ATX and electronic

lamp ballasts.

Absolute Maximum Ratings T

= 25

C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FDA18N50 Unit

DSS

Drain-Source Voltage 500 V

Drain Current - Continuous (T

= 25C)

- Continuous (T

= 100C)

11.4

Drain Current - Pulsed

(Note 1)

76 A

GSS

Gate-Source voltage 30 V

Single Pulsed Avalanche Energy

(Note 2)

945 mJ

Avalanche Current (Note 1) 19 A

Repetitive Avalanche Energy (Note 1) 23 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3) 4.5 V/ns

Power Dissipation (T

= 25C)

- Derate above 25C

239

1.92

W/C

STG

Operating and Storage Temperature Range -55 to +150 C

Maximum Lead Temperature for Soldering Purpose,

1/8” from Case for 5 Seconds

300 C

Symbol Parameter FDA18N50 Unit

JC

Thermal Resistance, Junction-to-Case, Max. 0.52

C/W

JA

Thermal Resistance, Junction-to-Ambient, Max. 40

TO-3PN

Summary of content (8 pages)

PAGE 1
FDA18N50 N-Channel UniFETTM MOSFET 500 V, 19 A, 265 m Features Description • RDS(on) = 265 m (Max.) @ VGS = 10 V, ID = 9.5 A UniFETTM MOSFET is Fairchild Semiconductor’s high voltage MOSFET family based on planar stripe and DMOS technology. This MOSFET is tailored to reduce on-state resistance, and to provide better switching performance and higher avalanche energy strength.
PAGE 2
Device Marking Device Package Reel Size Tape Width Quantity FDA18N50 FDA18N50 TO-3PN Tube N/A 30 units Electrical Characteristics TC = 25oC unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max Unit 500 -- -- V Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0V, ID = 250A BVDSS / TJ Breakdown Voltage Temperature Coefficient ID = 250A, Referenced to 25C -- 0.
PAGE 3
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 2 1 10 ID, Drain Current [A] 10 ID, Drain Current [A] 10 VGS Top : 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V 2 0 10 o 150 C 1 10 o 25 C o -55 C * Notes : 1. 250s Pulse Test -1 * Notes : 1. VDS = 40V 2. 250s Pulse Test o 10 2. TC = 25 C 0 -1 0 10 10 1 10 10 2 4 6 10 2 10 0.6 0.5 VGS = 10V 0.4 0.3 VGS = 20V 0.2 o 1 10 150oC o * Notes : 1. VGS = 0V 2.
PAGE 4
Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 3.0 1.1 1.0 * Notes : 1. VGS = 0 V 2. ID = 250A 0.9 0.8 -100 -50 0 50 100 2.5 RDS(ON), (Normalized) Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 150 2.0 1.5 1.0 * Notes : 1. VGS = 10 V 2. ID = 9.5 A 0.5 0.0 -100 200 o -50 0 TJ, Junction Temperature [ C] 50 100 150 200 o TJ, Junction Temperature [ C] Figure 9.
PAGE 5
FDA18N50 — N-Channel UniFETTM MOSFET Figure 12. Gate Charge Test Circuit & Waveform IG = const. Figure 13. Resistive Switching Test Circuit & Waveforms VDS RG RL VDS VDD VGS VGS DUT V 10V GS 90% 10% td(on) tr t on td(off) tf t off Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms VGS ©2006 Fairchild Semiconductor Corporation FDA18N50 Rev. C1 5 www.fairchildsemi.
PAGE 6
FDA18N50 — N-Channel UniFETTM MOSFET Figure 15.
PAGE 7
FDA18N50 — N-Channel UniFETTM MOSFET Mechanical Dimensions TO-3PN 3L Figure 16. 3LD, T03, Plastic, EIAJ SC-65 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.