Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDA50N50, MOSFET

November 2013

FDH50N50 / FDA50N50 — N-Channel UniFET

MOSFET

FDH50N50 / FDA50N50 Rev. C1

www.fairchildsemi.com

FDH50N50 / FDA50N50

N-Channel UniFET

MOSFET

500 V, 48 A, 105 mΩ

Features

•R

DS(on)

= 89 mΩ (Typ.) @ V

= 10 V, I

= 24 A

• Low Gate Charge (Typ. 105 nC)

• Low C

rss

(Typ. 45 pF)

• 100% Avalanche Tested

• Improved dv/dt Capability

Applications

• Lighting

• Uninterruptible Power Supply

• AC-DC Power Supply

Description

UniFET

MOSFET is Fairchild Semiconductor’s high voltage

MOSFET family based on planar stripe and DMOS technology.

This MOSFET is tailored to reduce on-state resistance, and to

provide better switching performance and higher avalanche

energy strength. This device family is suitable for switching

power converter applications such as power factor correction

(PFC), flat panel display (FPD) TV power, ATX and electronic

lamp ballasts.

TO-3PN

TO-247

Absolute Maximum Ratings T

= 25

C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FDH50N50_F133 / FDA50N50 Unit

DSS

Drain-Source Voltage 500 V

Drain Current - Continuous (T

= 25°C)

- Continuous (T

= 100°C)

30.8

Drain Current - Pulsed

(Note 1)

192 A

GSS

Gate-Source voltage ±20 V

Single Pulsed Avalanche Energy

(Note 2)

1868 mJ

Avalanche Current

(Note 1)

48 A

Repetitive Avalanche Energy

(Note 1)

62.5 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

20 V/ns

Power Dissipation (T

= 25°C)

- Derate Above 25°C

625

W/°C

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum Lead Temperature for Soldering,

1/8” from Case for 5 Seconds

300 °C

Symbol Parameter FDH50N50_F133 / FDA50N50 Unit

θJC

Thermal Resistance, Junction-to-Case, Max. 0.2

°C/W

θJA

Thermal Resistance, Junction-to-Ambient, Max. 40

Summary of content (10 pages)

PAGE 1
FDH50N50 / FDA50N50 N-Channel UniFETTM MOSFET 500 V, 48 A, 105 mΩ Features Description • RDS(on) = 89 mΩ (Typ.) @ VGS = 10 V, ID = 24 A UniFETTM MOSFET is Fairchild Semiconductor’s high voltage MOSFET family based on planar stripe and DMOS technology. This MOSFET is tailored to reduce on-state resistance, and to provide better switching performance and higher avalanche energy strength.
PAGE 2
FDH50N50_F133 Part Number Top Mark FDH50N50 Package TO-247 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 30 units FDA50N50 FDA50N50 TO-3PN Tube N/A N/A 30 units Electrical Characteristics Symbol TC = 25°C unless otherwise noted. Parameter Conditions Min. Typ. Max. Unit 500 -- -- V Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 μA ΔBVDSS / ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, Referenced to 25°C -- 0.
PAGE 3
Figure 1. On-Region Characteristics VGS 2 10 100 Top : 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V 1 10 ID , Drain Current [A] ID, Drain Current [A] Figure 2. Transfer Characteristics 0 10 10 o 150 Cٛ o 25 Cٛ o -55 Cٛ 1 Notes : 1. VDS = 40V Notes : 1. 250μs Pulse Test o 2. TC = 25 Cٛ 2. 250μs Pulse Test -1 10 -1 0 10 0.1 1 10 10 4 5 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 8 9 0.3 VGS = 10V 0.2 VGS = 20V 0.
PAGE 4
Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 2.5 RDS(ON), (Normalized) 1.1 1.0 Notes : 1. VGS = 0 V 0.9 2. ID = 250 μA Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 2.0 1.5 1.0 Notes : 1. VGS = 10 V 0.5 2. ID = 24 A 0.8 -100 -50 0 50 100 150 0.0 -100 200 -50 o 0 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 9.
PAGE 5
Figure 13. Typical Switching Losses vs. Gate Resistance Figure 14. Unclamped Inductive Switching Capability 1,000 100 Notes : 1. If R = 0 Ω tAV = (L)(IAS)/(1.3 Rated BVDSS - VDD) 2. If R ≠ 0 Ω tAV = (L/R)In[(IAS x R)/(1.3 Rated BVDSS - VDD)+1] 800 IAS, Avalanche Current [A] Energy [μJ] Eoff 600 Eon 400 Notes : 1. VDS = 400 V 200 2. VGS = 12 V o o Starting TJ = 150 C 10 Starting TJ = 25 C 3. ID = 25A o 0 4. TJ = 125 Cٛ 0 5 10 15 20 25 30 35 40 45 1 0.01 50 0.
PAGE 6
50KΩ 200nF 12V FDH50N50 / FDA50N50 — N-Channel UniFETTM MOSFET VGS Same Type as DUT Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 16. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on tf t off Figure 17. Resistive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp tp Time Figure 18.
PAGE 7
FDH50N50 / FDA50N50 — N-Channel UniFETTM MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 19.
PAGE 8
FDH50N50 / FDA50N50 — N-Channel UniFETTM MOSFET Mechanical Dimensions Figure 20. TO-247, Molded, 3-Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 9
FDH50N50 / FDA50N50 — N-Channel UniFETTM MOSFET Mechanical Dimensions Figure 21. TO3, 3-Lead, Plastic, EIAJ SC-65 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 10
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.