FDB035AN06A0 N-Channel PowerTrench® MOSFET 60 V, 80 A, 3.5 mΩ Features Applications • RDS(on) = 3.2 mΩ ( Typ.) @ VGS = 10 V, ID = 80 A • Synchronous Rectification for ATX / Server / Telecom PSU • QG(tot) = 95 nC ( Typ.
Device Marking FDB035AN06A0 Device FDB035AN06A0 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 60 - - - - 1 - - 250 VGS = ±20V - - ±100 nA VGS = VDS, ID = 250µA 2 - 4 V ID = 40A, VGS =
1.2 250 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 150 125 150 100 50 0 25 175 CURRENT LIMITED BY PACKAGE 200 50 75 TC , CASE TEMPERATURE (o C) 150 175 TC, CASE TEMPERATURE ( C) Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 1 ZθJC, NORMALIZED THERMAL IMPEDANCE 125 o Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 100 PDM 0.
2000 100 10µs 1000 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms 1 DC SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 10 STARTING TJ = 25oC IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100µs STARTING TJ = 150oC 10 If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.01 100 0.1 1 10 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5.
1.4 1.2 VGS = VDS, I D = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 0.2 -80 -40 0 40 80 120 160 1.1 1.0 0.9 200 ID = 250µA o -80 -40 TJ, JUNCTION TEMPERATURE ( C) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature VGS , GATE TO SOURCE VOLTAGE (V) 10 C, CAPACITANCE (pF) CISS = CGS + CGD COSS ≅ C DS + C GD 100 CRSS = CGD VGS = 0V, f = 1MHz 0.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.
.SUBCKT FDB035AN06A0 2 1 3 ; rev July 04, 2002 Ca 12 8 1.5e-9 Cb 15 14 1.5e-9 Cin 6 8 6.1e-9 DPLCAP 10 RSLC2 + GATE 1 Lgate 1 9 4.81e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.63e-9 RLGATE EVTEMP RGATE + 18 22 9 20 ESLC 11 50 EVTHRES + 19 8 6 21 EBREAK 16 + 17 18 - DBODY MWEAK MMED MSTRO CIN LSOURCE 8 7 RSOURCE RLgate 1 9 48.1 RLdrain 2 5 10 RLsource 3 7 46.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD DBREAK RDRAIN 6 8 ESG LGATE 5 51 - Ebreak 11 7 17 18 69.
rev July 4, 2002 template FDB035AN06A0 n2,n1,n3 = m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=2.4e-11,nl=1.04,rs=1.65e-3,trs1=2.7e-3,trs2=2e-7,cjo=4.35e-9,m=5.4e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.7e-9,isl=10e-30,nl=10,m=0.47) m..model mmedmod = (type=_n,vto=3.3,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.00,kp=275,is=1e-30, tox=1) LDRAIN m..model mweakmod = (type=_n,vto=2.72,kp=0.
th REV 23 July 4, 2002 JUNCTION FDB035AN06A0T CTHERM1 TH 6 6.45e-3 CTHERM2 6 5 3e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 TL 1e-1 RTHERM1 CTHERM1 6 RTHERM1 TH 6 3.24e-3 RTHERM2 6 5 8.08e-3 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 1e-1 RTHERM5 3 2 1.1e-1 RTHERM6 2 TL 1.4e-1 RTHERM2 CTHERM2 5 SABER Thermal Model RTHERM3 SABER thermal model FDB035AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =6.45e-3 ctherm.ctherm2 6 5 =3e-2 ctherm.ctherm3 5 4 =1.
FDB035AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 22. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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